Spi_Cfg.h

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  /*****************************************************************************
    Project: SPI_CONFIG_J721E
    Date   : 2022-11-29 01:31:24
    This file is generated by EB Tresos
    Do not modify this file, otherwise the software may behave in unexpected way.
 ******************************************************************************/

#ifndef SPI_CFG_H_
#define SPI_CFG_H_

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include "Os.h"
#include "Dem.h"
#include "Det.h"
#include "Spi_Cbk.h"

#ifdef __cplusplus
extern "C" {
#endif

#define SPI_VARIANT_POST_BUILD  (STD_ON)

#define SPI_CHANNELBUFFERS          (SPI_IB_EB)

#define SPI_IB_MAX_LENGTH           (64U)

#define SPI_DEV_ERROR_DETECT        (STD_ON)

#define SPI_JOB_LOG                 (STD_ON)

#define SPI_MAX_JOB_LOG             (100U)












#define SPI_MAX_HW_DMA_UNIT         (0U)

#define SPI_DMA_ENABLE              (STD_OFF)

/*
 * Scalability levels
 */
#define SPI_LEVEL_0                     (0U)

#define SPI_LEVEL_1                     (1U)

#define SPI_LEVEL_2                     (2U)

#define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT    (STD_OFF)

#define SPI_SCALEABILITY            (SPI_LEVEL_2)

#define SPI_VERSION_INFO_API        (STD_ON)

#define SPI_HW_STATUS_API           (STD_ON)

#define SPI_CANCEL_API              (STD_ON)

/*
 * All below macros are used for static memory allocation and can be changed to
 * match the usecase requirements.
 */
#define SPI_MAX_CHANNELS_PER_JOB    (1U)

#define SPI_MAX_JOBS_PER_SEQ        (1U)

#define SPI_MAX_CHANNELS            (1U)

#define SPI_MAX_JOBS                (1U)

#define SPI_MAX_SEQ                 (1U)

#define SPI_MAX_HW_UNIT             (8U)

#define SPI_MAX_EXT_DEV             (11U)

/*
 All below macros are used for enabling the ISR for a particular hardware.
 */

#define SPI_UNIT_MCU_MCSPI0_ACTIVE      (STD_ON)

#define SPI_UNIT_MCU_MCSPI1_ACTIVE      (STD_ON)

#define SPI_UNIT_MCU_MCSPI2_ACTIVE      (STD_ON)

#define SPI_UNIT_MCSPI0_ACTIVE      (STD_ON)

#define SPI_UNIT_MCSPI1_ACTIVE      (STD_ON)

#define SPI_UNIT_MCSPI2_ACTIVE      (STD_ON)

#define SPI_UNIT_MCSPI3_ACTIVE      (STD_ON)


#define SPI_UNIT_MCSPI4_ACTIVE      (STD_ON)

#define SPI_UNIT_MCSPI5_ACTIVE      (STD_OFF)

#define SPI_UNIT_MCSPI6_ACTIVE      (STD_OFF)

#define SPI_UNIT_MCSPI7_ACTIVE      (STD_OFF)













#define SPI_ISR_TYPE                (SPI_ISR_CAT1)

#define SPI_OS_COUNTER_ID           ((CounterType)OsCounter_0)

#define SPI_TIMEOUT_DURATION        (32000U)

#define SPI_REGISTER_READBACK_API   (STD_ON)

#define SPI_SAFETY_API   (STD_ON)

#define SpiConf_SpiChannel_SpiChannel_0   (0U)

#define SpiConf_SpiExternalDevice_CS0 (SPI_CS0)


#define SpiConf_SpiJob_SpiJob_0            (0U)

#define SpiConf_SpiSequence_SpiSequence_0  (0U)


#define SpiConf_SpiExternalDevice_HwUnitId0  (CSIB0)

#define SpiConf_SpiExternalDevice_HwUnitId1  (CSIB1)

#define SpiConf_SpiExternalDevice_HwUnitId2  (CSIB2)

#define SpiConf_SpiExternalDevice_HwUnitId3  (CSIB3)

#define SpiConf_SpiExternalDevice_HwUnitId4  (CSIB4)

#define SpiConf_SpiExternalDevice_HwUnitId5  (CSIB5)

#define SpiConf_SpiExternalDevice_HwUnitId6  (CSIB6)

#define SpiConf_SpiExternalDevice_HwUnitId7  (CSIB7)


#define DemConf_DemEventParameter_SPI_DEM_NO_EVENT (0xFFFFU)
#define SPI_DEM_NO_EVENT DemConf_DemEventParameter_SPI_DEM_NO_EVENT

#ifndef SPI_E_HARDWARE_ERROR

#define SPI_E_HARDWARE_ERROR        (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR)
#endif

#define SPI_UNIT_MCU_MCSPI0                 ((Spi_HWUnitType) CSIB0)

#define SPI_UNIT_MCU_MCSPI1                 ((Spi_HWUnitType) CSIB1)

#define SPI_UNIT_MCU_MCSPI2                 ((Spi_HWUnitType) CSIB2)

#define SPI_UNIT_MCSPI0                     ((Spi_HWUnitType) CSIB3)

#define SPI_UNIT_MCSPI1                     ((Spi_HWUnitType) CSIB4)

#define SPI_UNIT_MCSPI2                     ((Spi_HWUnitType) CSIB5)

#define SPI_UNIT_MCSPI3                     ((Spi_HWUnitType) CSIB6)

#define SPI_UNIT_MCSPI4                     ((Spi_HWUnitType) CSIB7)

#define SPI_UNIT_MCSPI5                     ((Spi_HWUnitType) CSIB8)

#define SPI_UNIT_MCSPI6                     ((Spi_HWUnitType) CSIB9)

#define SPI_UNIT_MCSPI7                     ((Spi_HWUnitType) CSIB10)
/* @} */

#define SPI_HW_UNIT_CNT                 (11U)

extern const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT];

/* @} */

/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */




typedef enum
{
    CSIB0 = 0U,
    CSIB1,
    CSIB2,
    CSIB3,
    CSIB4,
    CSIB5,
    CSIB6,
    CSIB7,
    CSIB8,
    CSIB9,
    CSIB10,
} Spi_HwUnitType;

extern void SpiApp_wbInvCache(uint8 *buf, uint16 len);
extern void SpiApp_wbCache(uint8 *buf, uint16 len);
extern void SpiApp_invCache(uint8 *buf, uint16 len);



extern const struct Spi_ConfigType_s SpiDriver;


/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(void);

FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1TxRx(void);

FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi2TxRx(void);

FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi3TxRx(void);

FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi4TxRx(void);

FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi5TxRx(void);

FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi6TxRx(void);

FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi7TxRx(void);





#ifdef __cplusplus
}
#endif

#endif  /* #ifndef SPI_CFG_H_ */

/* @} */