PDK API Guide for J721E
CacheP.h
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32 
50 #ifndef ti_osal_CacheP__include
51 #define ti_osal_CacheP__include
52 
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56 
57 #include <stdint.h>
58 #include <stdbool.h>
59 #include <stddef.h>
60 
69 typedef uint32_t Osal_CacheP_isCoherent;
71 #define OSAL_CACHEP_COHERENT ((uint32_t) 0U)
72 
73 #define OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U)
74 /* @} */
75 
85 typedef uint32_t CacheP_Mar;
87 #define CacheP_Mar_DISABLE (0U)
88 
89 #define CacheP_Mar_ENABLE (1U)
90 /* @} */
91 
100 extern void CacheP_wb(const void * addr, uint32_t size);
101 
102 
111 extern void CacheP_Inv(const void * addr, uint32_t size);
112 
113 
122 extern void CacheP_wbInv(const void * addr, uint32_t size);
123 
134 void CacheP_fenceCpu2Dma(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent);
135 
146 void CacheP_fenceDma2Cpu(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent);
147 
160 void CacheP_setMar(void *baseAddr, uint32_t size, uint32_t value);
161 
172 uint32_t CacheP_getMar(void *baseAddr);
173 
174 #ifdef __cplusplus
175 }
176 #endif
177 
178 #endif /* ti_osal_CacheP__include */
179 /* @} */
void CacheP_fenceDma2Cpu(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
Function to call before reading the memory to CPU after DMA operations.
uint32_t Osal_CacheP_isCoherent
This enumerator defines the cache coherent types.
Definition: CacheP.h:69
void CacheP_wb(const void *addr, uint32_t size)
Function to write back cache lines.
void CacheP_wbInv(const void *addr, uint32_t size)
Function to write back and invalidate cache lines.
uint32_t value
Definition: tisci_otp_revision.h:199
void CacheP_Inv(const void *addr, uint32_t size)
Function to invalidate cache lines.
void CacheP_fenceCpu2Dma(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
Function to call before handing over the memory buffer to DMA from CPU.
uint64_t addr
Definition: csl_udmap_tr.h:216
uint32_t CacheP_getMar(void *baseAddr)
Get MAR attribute for a region of 16MB.
uint32_t CacheP_Mar
This enumerator defines the MAR register setting types.
Definition: CacheP.h:85
void CacheP_setMar(void *baseAddr, uint32_t size, uint32_t value)
Set MAR attribute for a memory range.
uint16_t size
Definition: tisci_boardcfg.h:112