mcspi.h

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/*
 *  Copyright (C) 2013 - 2017 Texas Instruments Incorporated - www.ti.com
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
#ifndef MCSPI_H_
#define MCSPI_H_

#ifdef __cplusplus
extern "C"
{
#endif

/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include <ti/csl/cslr_mcspi.h>
#include <ti/csl/hw_types.h>

/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */

/*
 * \name Values used to determine the channel number used for McSPI
 * communication.
 * @{
 */
#define MCSPI_CHANNEL_0                (0U)

#define MCSPI_CHANNEL_1                (1U)

#define MCSPI_CHANNEL_2                (2U)

#define MCSPI_CHANNEL_3                (3U)
/* @} */

/*
 * \name Values of polarity and phase of SPICLK that are used to configure the
 * clock value in various modes of operation.
 * @{
 */
#define MCSPI_CLK_MODE_0            (((uint32_t) MCSPI_CH0CONF_POL_ACTIVEHIGH \
                                      << MCSPI_CH0CONF_POL_SHIFT) |           \
                                     MCSPI_CH0CONF_PHA_ODD)

#define MCSPI_CLK_MODE_1            (((uint32_t) MCSPI_CH0CONF_POL_ACTIVEHIGH \
                                      << MCSPI_CH0CONF_POL_SHIFT) |           \
                                     MCSPI_CH0CONF_PHA_EVEN)

#define MCSPI_CLK_MODE_2            (((uint32_t) MCSPI_CH0CONF_POL_ACTIVELOW << \
                                      MCSPI_CH0CONF_POL_SHIFT) |                \
                                     MCSPI_CH0CONF_PHA_ODD)

#define MCSPI_CLK_MODE_3            (((uint32_t) MCSPI_CH0CONF_POL_ACTIVELOW << \
                                      MCSPI_CH0CONF_POL_SHIFT) |                \
                                     MCSPI_CH0CONF_PHA_EVEN)
/* @} */

/*
 * \name McSPI Register Offset for MCSPI_CHxCONF, MCSPI_CHxSTAT, MCSPI_CHxCTRL,
 * MCSPI_TXx and MCSPI_RXx register set.
 * @{
 */
#define MCSPI_REG_OFFSET            (0x14U)

#define MCSPI_CHCONF(x)             ((uint32_t) MCSPI_CH0CONF + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

#define MCSPI_CHSTAT(x)             ((uint32_t) MCSPI_CH0STAT + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

#define MCSPI_CHCTRL(x)             ((uint32_t) MCSPI_CH0CTRL + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

#define MCSPI_CHTX(x)               ((uint32_t) MCSPI_TX0 + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))

#define MCSPI_CHRX(x)               ((uint32_t) MCSPI_RX0 + \
                                     (uint32_t) ((uint32_t) MCSPI_REG_OFFSET * \
                                     ((uint32_t) (x))))
/* @} */

/*
 * \name Values of minumum & maximum word lengths that is valid for SPI channel
 * config.
 * @{
 */
#define MCSPI_WORD_LENGTH_MIN            ((uint32_t) 4U)

#define MCSPI_WORD_LENGTH_MAX            ((uint32_t) 32U)
/* @} */

/*
 * \name Values used to set the word length for McSPI communication.
 * 'n' can take values only between 4 <= n <= 32.
 * @{
 */
#define MCSPI_WORD_LENGTH(n)        ((((uint32_t) (n)) - \
                                      (uint32_t) 1U) << MCSPI_CH0CONF_WL_SHIFT)
/* @} */

/*
 * \name Values used to configure the chip select time control(TCS).
 * @{
 */
#define MCSPI_CS_TCS_0PNT5_CLK      ((uint32_t) MCSPI_CH0CONF_TCS0_ZEROCYCLEDLY \
                                     << MCSPI_CH0CONF_TCS0_SHIFT)

#define MCSPI_CS_TCS_1PNT5_CLK      ((uint32_t) MCSPI_CH0CONF_TCS0_ONECYCLEDLY \
                                     << MCSPI_CH0CONF_TCS0_SHIFT)

#define MCSPI_CS_TCS_2PNT5_CLK      ((uint32_t) MCSPI_CH0CONF_TCS0_TWOCYCLEDLY \
                                     << MCSPI_CH0CONF_TCS0_SHIFT)

#define MCSPI_CS_TCS_3PNT5_CLK      ((uint32_t)                          \
                                     MCSPI_CH0CONF_TCS0_THREECYCLEDLY << \
                                     MCSPI_CH0CONF_TCS0_SHIFT)
/* @} */

/*
 * \name Value used to set the polarity for start bit for McSPI communication.
 * @{
 */
#define MCSPI_START_BIT_POL_LOW     (MCSPI_CH0CONF_SBPOL_LOWLEVEL)

#define MCSPI_START_BIT_POL_HIGH    (MCSPI_CH0CONF_SBPOL_HIGHLEVEL)
/* @} */

/*
 * \name Values used to determine transmit/receive modes of McSPI peripheral in
 * master mode.
 * @{
 */
#define MCSPI_TX_RX_MODE            ((uint32_t) MCSPI_CH0CONF_TRM_TRANSRECEI << \
                                     MCSPI_CH0CONF_TRM_SHIFT)

#define MCSPI_RX_ONLY_MODE          ((uint32_t) MCSPI_CH0CONF_TRM_RECEIVONLY << \
                                     MCSPI_CH0CONF_TRM_SHIFT)

#define MCSPI_TX_ONLY_MODE          ((uint32_t) MCSPI_CH0CONF_TRM_TRANSONLY << \
                                     MCSPI_CH0CONF_TRM_SHIFT)
/* @} */

/*
 * \name Values used to configure communication on data line pins.
 * @{
 */
#define MCSPI_DATA_LINE_COMM_MODE_0  (((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

#define MCSPI_DATA_LINE_COMM_MODE_1  (((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED   \
                                       << MCSPI_CH0CONF_DPE0_SHIFT))

#define MCSPI_DATA_LINE_COMM_MODE_2  (((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED   \
                                       << MCSPI_CH0CONF_DPE1_SHIFT) |           \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

#define MCSPI_DATA_LINE_COMM_MODE_3  (((uint32_t) MCSPI_CH0CONF_IS_LINE0 <<   \
                                       MCSPI_CH0CONF_IS_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED \
                                       << MCSPI_CH0CONF_DPE1_SHIFT) |         \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED \
                                       << MCSPI_CH0CONF_DPE0_SHIFT))

#define MCSPI_DATA_LINE_COMM_MODE_4  (((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

#define MCSPI_DATA_LINE_COMM_MODE_5  (((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_ENABLED << \
                                       MCSPI_CH0CONF_DPE1_SHIFT) |              \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED   \
                                       << MCSPI_CH0CONF_DPE0_SHIFT))

#define MCSPI_DATA_LINE_COMM_MODE_6  (((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<     \
                                       MCSPI_CH0CONF_IS_SHIFT) |                \
                                      ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED   \
                                       << MCSPI_CH0CONF_DPE1_SHIFT) |           \
                                      ((uint32_t) MCSPI_CH0CONF_DPE0_ENABLED << \
                                       MCSPI_CH0CONF_DPE0_SHIFT))

#define MCSPI_DATA_LINE_COMM_MODE_7   (((uint32_t) MCSPI_CH0CONF_IS_LINE1 <<   \
                                        MCSPI_CH0CONF_IS_SHIFT) |              \
                                       ((uint32_t) MCSPI_CH0CONF_DPE1_DISABLED \
                                        << MCSPI_CH0CONF_DPE1_SHIFT) |         \
                                       ((uint32_t) MCSPI_CH0CONF_DPE0_DISABLED \
                                        << MCSPI_CH0CONF_DPE0_SHIFT))
/* @} */

/*
 * \name Values used to enable/disable the Tx/Rx FIFOs of McSPI peripheral.
 * @{
 */
#define MCSPI_RX_FIFO_ENABLE         ((uint32_t) MCSPI_CH0CONF_FFER_FFENABLED \
                                      <<                                      \
                                      MCSPI_CH0CONF_FFER_SHIFT)

#define MCSPI_RX_FIFO_DISABLE        ((uint32_t) MCSPI_CH0CONF_FFER_FFDISABLED \
                                      << MCSPI_CH0CONF_FFER_SHIFT)

#define MCSPI_TX_FIFO_ENABLE         ((uint32_t) MCSPI_CH0CONF_FFEW_FFENABLED \
                                      << MCSPI_CH0CONF_FFEW_SHIFT)

#define MCSPI_TX_FIFO_DISABLE        ((uint32_t) MCSPI_CH0CONF_FFEW_FFDISABLED \
                                      << MCSPI_CH0CONF_FFEW_SHIFT)
/* @} */

/*
 * \name Values used to enable/disable the read/write DMA events of McSPI
 * peripheral.
 * @{
 */
#define MCSPI_DMA_RX_EVENT           ((uint32_t) MCSPI_CH0CONF_DMAR_ENABLED << \
                                      MCSPI_CH0CONF_DMAR_SHIFT)

#define MCSPI_DMA_TX_EVENT           ((uint32_t) MCSPI_CH0CONF_DMAW_ENABLED << \
                                      MCSPI_CH0CONF_DMAW_SHIFT)
/* @} */

/*
 * \name Values that can be passed to enable/disable/clear status of  the
 * various interrupts of McSPI peripheral.
 * These macros can also be used to check the status obtained from
 * 'McSPIIntStatusGet' API.
 * @{
 */
#define MCSPI_INT_TX_EMPTY(chan)     ((uint32_t)                               \
                                      MCSPI_IRQENABLE_TX0_EMPTY_ENABLE_MASK << \
                                      ((chan) * 4U))

#define MCSPI_INT_TX_UNDERFLOW(chan) ((uint32_t)                                \
                                      MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE_MASK \
                                      << ((chan) * 4U))

#define MCSPI_INT_RX_FULL(chan)      ((uint32_t)                              \
                                      MCSPI_IRQENABLE_RX0_FULL_ENABLE_MASK << \
                                      ((chan) * 4U))

#define MCSPI_INT_RX0_OVERFLOW       ((uint32_t) \
                                      MCSPI_IRQSTATUS_RX0_OVERFLOW_MASK)

#define MCSPI_INT_EOWKE              ((uint32_t)                               \
                                      MCSPI_IRQENABLE_EOW_ENABLE_IRQENABLED << \
                                      MCSPI_IRQENABLE_EOW_ENABLE_SHIFT)
/* @} */

/*
 * \name Values used to enable initial delay for first transfer from McSPI
 * peripheral.
 * @{
 */
#define MCSPI_INITDLY_0              ((uint32_t)                         \
                                      MCSPI_MODULCTRL_INITDLY_NODELAY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

#define MCSPI_INITDLY_4              ((uint32_t)                         \
                                      MCSPI_MODULCTRL_INITDLY_4CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

#define MCSPI_INITDLY_8              ((uint32_t)                         \
                                      MCSPI_MODULCTRL_INITDLY_8CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

#define MCSPI_INITDLY_16             ((uint32_t)                          \
                                      MCSPI_MODULCTRL_INITDLY_16CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)

#define MCSPI_INITDLY_32             ((uint32_t)                          \
                                      MCSPI_MODULCTRL_INITDLY_32CLKDLY << \
                                      MCSPI_MODULCTRL_INITDLY_SHIFT)
/* @} */

/*
 * \name Values used to check the status of McSPI channel status registers and
 * FIFO.
 * @{
 */
#define MCSPI_CH_STAT_RXS_FULL       ((uint32_t) MCSPI_CH0STAT_RXS_FULL << \
                                      MCSPI_CH0STAT_RXS_SHIFT)

#define MCSPI_CH_STAT_TXS_EMPTY      ((uint32_t) MCSPI_CH0STAT_TXS_EMPTY << \
                                      MCSPI_CH0STAT_TXS_SHIFT)

#define MCSPI_CH_STAT_EOT            ((uint32_t) MCSPI_CH0STAT_EOT_COMPLETED << \
                                      MCSPI_CH0STAT_EOT_SHIFT)

#define MCSPI_CH_TXFFE               ((uint32_t) MCSPI_CH0STAT_TXFFE_EMPTY << \
                                      MCSPI_CH0STAT_TXFFE_SHIFT)

#define MCSPI_CH_TXFFF               ((uint32_t) MCSPI_CH0STAT_TXFFF_FULL << \
                                      MCSPI_CH0STAT_TXFFF_SHIFT)

#define MCSPI_CH_RXFFE               ((uint32_t) MCSPI_CH0STAT_RXFFE_EMPTY << \
                                      MCSPI_CH0STAT_RXFFE_SHIFT)

#define MCSPI_CH_RXFFF               ((uint32_t) MCSPI_CH0STAT_RXFFF_FULL << \
                                      MCSPI_CH0STAT_RXFFF_SHIFT)
/* @} */

/*
 * \name Value used to enable/disable multiple word ocp access.
 * @{
 */
#define MCSPI_MOA_ENABLE            ((uint32_t) MCSPI_MODULCTRL_MOA_MULTIACCES \
                                     << MCSPI_MODULCTRL_MOA_SHIFT)

#define MCSPI_MOA_DISABLE           ((uint32_t)                           \
                                     MCSPI_MODULCTRL_MOA_NOMULTIACCESS << \
                                     MCSPI_MODULCTRL_MOA_SHIFT)
/* @} */

/*
 * \name Value used to configure to single/multiple channel.
 * @{
 */
#define MCSPI_SINGLE_CH            ((uint32_t) MCSPI_MODULCTRL_SINGLE_SINGLE << \
                                    MCSPI_MODULCTRL_SINGLE_SHIFT)

#define MCSPI_MULTI_CH            ((uint32_t) MCSPI_MODULCTRL_SINGLE_MULTI << \
                                   MCSPI_MODULCTRL_SINGLE_SHIFT)
/* @} */

/*
 * \name Value used to configure the Chip select Polarity
 * @{
 */
#define MCSPI_CS_POL_HIGH          ((uint32_t) MCSPI_CH0CONF_EPOL_ACTIVEHIGH << \
                                    MCSPI_CH0CONF_EPOL_SHIFT)

#define MCSPI_CS_POL_LOW           ((uint32_t) MCSPI_CH0CONF_EPOL_ACTIVELOW << \
                                    MCSPI_CH0CONF_EPOL_SHIFT)
/* @} */

/*
 * \name Value used to enable/disable FDAA operation of McSPI peripheral.
 * @{
 */
#define MCSPI_FDAA_DISABLE           ((uint32_t)                          \
                                      MCSPI_MODULCTRL_FDAA_SHADOWREGEN << \
                                      MCSPI_MODULCTRL_FDAA_SHIFT)

#define MCSPI_FDAA_ENABLE            ((uint32_t)                          \
                                      MCSPI_MODULCTRL_FDAA_NOSHADOWREG << \
                                      MCSPI_MODULCTRL_FDAA_SHIFT)
/* @} */

/*
 * \name Values used to configure the SYSCONFIG
 * @{
 */
#define MCSPI_CLOCKS_OCP_OFF_FUNC_OFF ((uint32_t)                            \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_NONE << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

#define MCSPI_CLOCKS_OCP_ON_FUNC_OFF  ((uint32_t)                           \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_OCP << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

#define MCSPI_CLOCKS_OCP_OFF_FUNC_ON  ((uint32_t)                            \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_FUNC << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

#define MCSPI_CLOCKS_OCP_ON_FUNC_ON   ((uint32_t)                            \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_BOTH << \
                                       MCSPI_SYSCONFIG_CLOCKACTIVITY_SHIFT)

#define MCSPI_SIDLEMODE_FORCE         ((uint32_t)                         \
                                       MCSPI_SYSCONFIG_SIDLEMODE_FORCE << \
                                       MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)

#define MCSPI_SIDLEMODE_NO            ((uint32_t) MCSPI_SYSCONFIG_SIDLEMODE_NO \
                                       << MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)

#define MCSPI_SIDLEMODE_SMART_IDLE    ((uint32_t)                         \
                                       MCSPI_SYSCONFIG_SIDLEMODE_SMART << \
                                       MCSPI_SYSCONFIG_SIDLEMODE_SHIFT)

/*TI_INSPECTED 67 X : MISRAC_2012_D.4.5
 * "Reason - LDRA tool issue : Not able to understand unique Identifier with
 *  "-" " */
#define MCSPI_WAKEUP_ENABLE           ((uint32_t) MCSPI_SYSCONFIG_ENAWAKEUP_ON \
                                       << MCSPI_SYSCONFIG_ENAWAKEUP_SHIFT)

#define MCSPI_WAKEUP_DISABLE          ((uint32_t)                            \
                                       MCSPI_SYSCONFIG_ENAWAKEUP_NOWAKEUP << \
                                       MCSPI_SYSCONFIG_ENAWAKEUP_SHIFT)

#define MCSPI_AUTOIDLE_ON             ((uint32_t) MCSPI_SYSCONFIG_AUTOIDLE_ON \
                                       << MCSPI_SYSCONFIG_AUTOIDLE_SHIFT)

#define MCSPI_AUTOIDLE_OFF            ((uint32_t) MCSPI_SYSCONFIG_AUTOIDLE_OFF \
                                       << MCSPI_SYSCONFIG_AUTOIDLE_SHIFT)
/* @} */

/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */

extern void McSPIClkConfig(uint32_t baseAddr,
                           uint32_t spiInClk,
                           uint32_t spiOutClk,
                           uint32_t chNum,
                           uint32_t clkMode);
extern void McSPIWordLengthSet(uint32_t baseAddr,
                               uint32_t wordLength,
                               uint32_t chNum);

extern void McSPICSEnable(uint32_t baseAddr);

extern void McSPICSDisable(uint32_t baseAddr);

extern void McSPICSPolarityConfig(uint32_t baseAddr,
                                  uint32_t spiEnPol,
                                  uint32_t chNum);

extern void McSPICSTimeControlSet(uint32_t baseAddr,
                                  uint32_t csTimeControl,
                                  uint32_t chNum);

static inline void McSPICSAssert(uint32_t baseAddr, uint32_t chNum);

static inline void McSPICSDeAssert(uint32_t baseAddr, uint32_t chNum);

extern void McSPIStartBitEnable(uint32_t baseAddr, uint32_t chNum);

extern void McSPIStartBitPolarityConfig(uint32_t baseAddr,
                                        uint32_t startBitPol,
                                        uint32_t chNum);

extern void McSPIStartBitDisable(uint32_t baseAddr, uint32_t chNum);

extern void McSPIMasterModeEnable(uint32_t baseAddr);

extern void McSPISlaveModeEnable(uint32_t baseAddr);

extern uint32_t McSPIMasterModeConfig(uint32_t baseAddr,
                                      uint32_t channelMode,
                                      uint32_t trMode,
                                      uint32_t pinMode,
                                      uint32_t chNum);

static inline void McSPIChannelEnable(uint32_t baseAddr, uint32_t chNum);

static inline void McSPIChannelDisable(uint32_t baseAddr, uint32_t chNum);

extern void McSPIReset(uint32_t baseAddr);

extern void McSPITurboModeEnable(uint32_t baseAddr, uint32_t chNum);

extern void McSPITurboModeDisable(uint32_t baseAddr, uint32_t chNum);

extern void McSPITxFIFOConfig(uint32_t baseAddr,
                              uint32_t txFifo,
                              uint32_t chNum);

extern void McSPIRxFIFOConfig(uint32_t baseAddr,
                              uint32_t rxFifo,
                              uint32_t chNum);

extern void McSPIFIFOTrigLvlSet(uint32_t baseAddr,
                                uint8_t  afl,
                                uint8_t  ael,
                                uint32_t trMode);

extern void McSPIWordCountSet(uint32_t baseAddr, uint16_t wCnt);

extern void McSPIDMAEnable(uint32_t baseAddr,
                           uint32_t dmaFlags,
                           uint32_t chNum);

extern void McSPIDMADisable(uint32_t baseAddr,
                            uint32_t dmaFlags,
                            uint32_t chNum);

extern void McSPIIntEnable(uint32_t baseAddr, uint32_t intFlags);

extern void McSPIIntDisable(uint32_t baseAddr, uint32_t intFlags);

extern void McSPIInitDelayConfig(uint32_t baseAddr, uint32_t initDelay);

static inline void McSPITransmitData(uint32_t baseAddr,
                              uint32_t txData,
                              uint32_t chNum);

extern uint32_t McSPIReceiveData(uint32_t baseAddr, uint32_t chNum);

extern uint32_t McSPIIntStatusGet(uint32_t baseAddr);

extern void McSPIIntStatusClear(uint32_t baseAddr, uint32_t intFlags);

static inline uint32_t McSPIChannelStatusGet(uint32_t baseAddr, uint32_t chNum);

extern void McSPIMultipleWordAccessConfig(uint32_t baseAddr, uint32_t moa);

extern void McSPIFIFODatManagementConfig(uint32_t baseAddr, uint32_t fdaa);

extern void MCSPISysConfigSetup(uint32_t baseAddr,
                                uint32_t clockActivity,
                                uint32_t sidleMode,
                                uint32_t wakeUp,
                                uint32_t autoIdle);

extern uint32_t MCSPIPinDirSet(uint32_t baseAddr,
                               uint32_t trMode,
                               uint32_t pinMode,
                               uint32_t chNum);

extern void MCSPISingleChModeEnable(uint32_t baseAddr);

extern void MCSPIMultiChModeEnable(uint32_t baseAddr);

extern void McSPISetSlaveChipSel(uint32_t baseAddr,
                                 uint32_t chNum,
                                 uint32_t slaveChipSel);

static inline uint32_t McSPIGetChannelCtrl(uint32_t baseAddr, uint32_t chNum);

static inline void McSPISetChannelCtrl(uint32_t baseAddr, uint32_t chNum, uint32_t regVal);

static inline uint32_t McSPIGetChannelConf(uint32_t baseAddr, uint32_t chNum);

static inline void McSPISetChannelConf(uint32_t baseAddr, uint32_t chNum, uint32_t regVal);

/* ========================================================================== */
/*                   Static Inline Function Definitions                       */
/* ========================================================================== */

static inline uint32_t McSPIChannelStatusGet(uint32_t baseAddr, uint32_t chNum)
{
    /* Return the status from MCSPI_CHSTAT register. */
    return (HW_RD_REG32(baseAddr + MCSPI_CHSTAT(chNum)));
}

/*TI_INSPECTED 65 D : MISRAC_2012_R.2.2
 * "Reason - Void function does have side effect. It enables the channel
 *  register field in McSPI register" */
static inline void McSPIChannelEnable(uint32_t baseAddr, uint32_t chNum)
{
    /* Set the EN field of MCSPI_CHCTRL register. */
    HW_WR_FIELD32(
        baseAddr + MCSPI_CHCTRL(chNum),
        MCSPI_CH0CTRL_EN,
        MCSPI_CH0CTRL_EN_ACT);

}

/*TI_INSPECTED 65 D : MISRAC_2012_R.2.2
 * "Reason - Void function does have side effect. It is setting the force bit
 *  register field in McSPI register for McSPI channel configiration" */
static inline void McSPICSAssert(uint32_t baseAddr, uint32_t chNum)
{
    /* Set the FORCE bit of MCSPI_CHCONF register. */
    HW_WR_FIELD32(
        baseAddr + MCSPI_CHCONF(chNum),
        MCSPI_CH0CONF_FORCE,
        MCSPI_CH0CONF_FORCE_ASSERT);
}

/*TI_INSPECTED 65 D : MISRAC_2012_R.2.2
 * "Reason - Void function does have side effect. It clears the force bit
 *  register field in McSPI register for McSPI channel configiration" */
static inline void McSPICSDeAssert(uint32_t baseAddr, uint32_t chNum)
{
    /* Clear the FORCE bit of MCSPI_CHCONF register. */
    HW_WR_FIELD32(
        baseAddr + MCSPI_CHCONF(chNum),
        MCSPI_CH0CONF_FORCE,
        MCSPI_CH0CONF_FORCE_DEASSERT);
}

/*TI_INSPECTED 65 D : MISRAC_2012_R.2.2
 * "Reason - Void function does have side effect. It disables the channel
 *  register field in McSPI register" */
static inline void McSPIChannelDisable(uint32_t baseAddr, uint32_t chNum)
{
    /* Clear the EN field of MCSPI_CHCTRL register. */
    HW_WR_FIELD32(
        baseAddr + MCSPI_CHCTRL(chNum),
        MCSPI_CH0CTRL_EN,
        MCSPI_CH0CTRL_EN_NACT);
}

/*TI_INSPECTED 1 D 1: MISRA-C:2012_R.2.7
 * "Reason - Ensured procedure parameter is used" */
static inline void McSPITransmitData(uint32_t baseAddr,
                       uint32_t txData,
                       uint32_t chNum)
{
    /* Load the MCSPI_TX register with the data to be transmitted */
    HW_WR_REG32(baseAddr + MCSPI_CHTX(chNum), txData);
}

static inline uint32_t McSPIGetChannelCtrl(uint32_t baseAddr, uint32_t chNum)
{
    return HW_RD_REG32(baseAddr + MCSPI_CHCTRL(chNum));
}

static inline void McSPISetChannelCtrl(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
{
    HW_WR_REG32(baseAddr + MCSPI_CHCTRL(chNum), regVal);
}

static inline uint32_t McSPIGetChannelConf(uint32_t baseAddr, uint32_t chNum)
{
    return HW_RD_REG32(baseAddr + MCSPI_CHCONF(chNum));
}

static inline void McSPISetChannelConf(uint32_t baseAddr, uint32_t chNum, uint32_t regVal)
{
    HW_WR_REG32(baseAddr + MCSPI_CHCONF(chNum), regVal);
}

#ifdef __cplusplus
}
#endif
#endif  /* MCSPI_H_ */

/********************************* End of file ******************************/