PDK API Guide for J721E
tps65941.h
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33 
54 /* @} */
55 
56 #ifndef _TPS65941_H_
57 #define _TPS65941_H_
58 
59 #include <stdio.h>
60 #include <stdint.h>
61 #include <stdlib.h>
62 #include <string.h>
63 
64 #include <ti/drv/i2c/I2C.h>
65 
66 #include <ti/board/board.h>
67 
68 #include <ti/board/src/devices/common/common.h>
69 
70 #ifdef __cplusplus
71 extern "C" {
72 #endif
73 
87 #define BOARD_TPS65941_GPIO1_CONF (0x31U)
88 #define BOARD_TPS65941_GPIO2_CONF (0x32U)
89 #define BOARD_TPS65941_GPIO3_CONF (0x33U)
90 #define BOARD_TPS65941_GPIO4_CONF (0x34U)
91 #define BOARD_TPS65941_GPIO5_CONF (0x35U)
92 #define BOARD_TPS65941_GPIO6_CONF (0x36U)
93 #define BOARD_TPS65941_GPIO7_CONF (0x37U)
94 #define BOARD_TPS65941_GPIO8_CONF (0x38U)
95 #define BOARD_TPS65941_GPIO9_CONF (0x39U)
96 #define BOARD_TPS65941_GPIO10_CONF (0x3AU)
97 #define BOARD_TPS65941_GPIO11_CONF (0x3BU)
98 #define BOARD_TPS65941_NPWRON_CONF (0x3CU)
99 #define BOARD_TPS65941_GPIO_OUT_1 (0x3DU)
100 #define BOARD_TPS65941_GPIO_OUT_2 (0x3EU)
101 #define BOARD_TPS65941_GPIO_IN_1 (0x3FU)
102 #define BOARD_TPS65941_GPIO_IN_2 (0x40U)
103 
105 #define BOARD_TPS65941_BUCK1_CTRL (0x04U)
106 #define BOARD_TPS65941_BUCK2_CTRL (0x06U)
107 #define BOARD_TPS65941_BUCK3_CTRL (0x08U)
108 #define BOARD_TPS65941_BUCK4_CTRL (0x0AU)
109 #define BOARD_TPS65941_BUCK5_CTRL (0x0CU)
110 #define BOARD_TPS65941_BUCK1_CONF (0x05U)
111 #define BOARD_TPS65941_BUCK2_CONF (0x07U)
112 #define BOARD_TPS65941_BUCK3_CONF (0x09U)
113 #define BOARD_TPS65941_BUCK4_CONF (0x0BU)
114 #define BOARD_TPS65941_BUCK5_CONF (0x0DU)
115 #define BOARD_TPS65941_BUCK1_VOUT_1 (0x0EU)
116 #define BOARD_TPS65941_BUCK1_VOUT_2 (0x0FU)
117 #define BOARD_TPS65941_BUCK2_VOUT_1 (0x10U)
118 #define BOARD_TPS65941_BUCK2_VOUT_2 (0x11U)
119 #define BOARD_TPS65941_BUCK3_VOUT_1 (0x12U)
120 #define BOARD_TPS65941_BUCK3_VOUT_2 (0x13U)
121 #define BOARD_TPS65941_BUCK4_VOUT_1 (0x14U)
122 #define BOARD_TPS65941_BUCK4_VOUT_2 (0x15U)
123 #define BOARD_TPS65941_BUCK5_VOUT_1 (0x16U)
124 #define BOARD_TPS65941_BUCK5_VOUT_2 (0x17U)
125 #define BOARD_TPS65941_BUCK1_PG_WIN (0x18U)
126 #define BOARD_TPS65941_BUCK2_PG_WIN (0x19U)
127 #define BOARD_TPS65941_BUCK3_PG_WIN (0x1AU)
128 #define BOARD_TPS65941_BUCK4_PG_WIN (0x1BU)
129 #define BOARD_TPS65941_BUCK5_PG_WIN (0x1CU)
130 
132 #define BOARD_TPS65941_LDO1_CTRL (0x1DU)
133 #define BOARD_TPS65941_LDO2_CTRL (0x1EU)
134 #define BOARD_TPS65941_LDO3_CTRL (0x1FU)
135 #define BOARD_TPS65941_LDO4_CTRL (0x20U)
136 #define BOARD_TPS65941_LDO1_VOUT (0x23U)
137 #define BOARD_TPS65941_LDO2_VOUT (0x24U)
138 #define BOARD_TPS65941_LDO3_VOUT (0x25U)
139 #define BOARD_TPS65941_LDO4_VOUT (0x26U)
140 #define BOARD_TPS65941_LDO1_PG_WIN (0x27U)
141 #define BOARD_TPS65941_LDO2_PG_WIN (0x28U)
142 #define BOARD_TPS65941_LDO3_PG_WIN (0x29U)
143 #define BOARD_TPS65941_LDO4_PG_WIN (0x2AU)
144 
146 #define BOARD_TPS65941_VCCA_VMON_CTRL (0x2BU)
147 #define BOARD_TPS65941_VCCA_PG_WINDOW (0x2CU)
148 
150 #define BOARD_TPS65941_BUCK_MASK (0x49)
151 #define BOARD_TPS65941_LDO_MASK (0x4C)
152 #define BOARD_TPS65941_GPIO_MASK (0x4F)
153 #define BOARD_TPS65941_STARTUP_MASK (0x52)
154 #define BOARD_TPS65941_MISC_WARN_MASK (0x53)
155 #define BOARD_TPS65941_MOD_ERR_MASK (0x54)
156 #define BOARD_TPS65941_FSM_ERR_MASK (0x56)
157 
159 #define BOARD_TPS65941_INT_TOP (0x5A)
160 #define BOARD_TPS65941_BUCK_INT (0x5C)
161 #define BOARD_TPS65941_LDO_VMON_INT (0x60)
162 #define BOARD_TPS65941_GPIO_INT (0x63)
163 #define BOARD_TPS65941_STARTUP_INT (0x65)
164 #define BOARD_TPS65941_MISC_INT (0x66)
165 #define BOARD_TPS65941_MOD_ERR_INT (0x67)
166 #define BOARD_TPS65941_SEV_ERR_INT (0x68)
167 #define BOARD_TPS65941_FSM_ERR_INT (0x69)
168 
170 #define BOARD_TPS65941_STAT_MISC (0x74U)
171 #define BOARD_TPS65941_STAT_MODERATE_ERR (0x75U)
172 #define BOARD_TPS65941_STAT_SEVERE_ERR (0x76U)
173 
175 #define BOARD_TPS65941_PGOOD_1 (0x78U)
176 #define BOARD_TPS65941_PGOOD_2 (0x79U)
177 #define BOARD_TPS65941_PGOOD_3 (0x7AU)
178 #define BOARD_TPS65941_PGOOD_4 (0x7BU)
179 
181 #define BOARD_TPS65941_CONFIG_1 (0x7DU)
182 #define BOARD_TPS65941_CONFIG_2 (0x7EU)
183 
185 #define BOARD_TPS65941_ESM_MCU_START (0x8FU)
186 #define BOARD_TPS65941_ESM_MCU_DELAY1 (0x90U)
187 #define BOARD_TPS65941_ESM_MCU_DELAY2 (0x91U)
188 #define BOARD_TPS65941_ESM_MCU_MODE_CFG (0x92U)
189 #define BOARD_TPS65941_ESM_MCU_HMAX (0x93U)
190 #define BOARD_TPS65941_ESM_MCU_HMIN (0x94U)
191 #define BOARD_TPS65941_ESM_MCU_LMAX (0x95U)
192 #define BOARD_TPS65941_ESM_MCU_LMIN (0x96U)
193 #define BOARD_TPS65941_ESM_MCU_ERR_CNT (0x97U)
194 #define BOARD_TPS65941_ESM_SOC_START (0x98U)
195 #define BOARD_TPS65941_ESM_SOC_DELAY1 (0x99U)
196 #define BOARD_TPS65941_ESM_SOC_DELAY2 (0x9AU)
197 #define BOARD_TPS65941_ESM_SOC_MODE_CFG (0x9BU)
198 #define BOARD_TPS65941_ESM_SOC_HMAX (0x9CU)
199 #define BOARD_TPS65941_ESM_SOC_HMIN (0x9DU)
200 #define BOARD_TPS65941_ESM_SOC_LMAX (0x9EU)
201 #define BOARD_TPS65941_ESM_SOC_LMIN (0x9FU)
202 #define BOARD_TPS65941_ESM_SOC_ERR_CNT (0xA0U)
203 
205 #define BOARD_TPS65941_RTC_SECONDS (0xB5U)
206 #define BOARD_TPS65941_RTC_MINUTES (0xB6U)
207 #define BOARD_TPS65941_RTC_HOURS (0xB7U)
208 #define BOARD_TPS65941_RTC_DAYS (0xB8U)
209 #define BOARD_TPS65941_RTC_MONTHS (0xB9U)
210 #define BOARD_TPS65941_RTC_YEARS (0xBAU)
211 #define BOARD_TPS65941_RTC_WEEKS (0xBBU)
212 
214 #define BOARD_TPS65941_ALARM_SECONDS (0xBCU)
215 #define BOARD_TPS65941_ALARM_MINUTES (0xBDU)
216 #define BOARD_TPS65941_ALARM_HOURS (0xBEU)
217 #define BOARD_TPS65941_ALARM_DAYS (0xBFU)
218 #define BOARD_TPS65941_ALARM_MONTHS (0xC0U)
219 #define BOARD_TPS65941_ALARM_YEARS (0xC1U)
220 
222 #define BOARD_TPS65941_RTC_CTRL_1 (0xC2U)
223 #define BOARD_TPS65941_RTC_CTRL_2 (0xC3U)
224 #define BOARD_TPS65941_RTC_STATUS (0xC4U)
225 #define BOARD_TPS65941_RTC_INTR (0xC5U)
226 
228 #define BOARD_TPS65941_WDT_ANSW_REG (0x01U)
229 #define BOARD_TPS65941_WDT_QUES_ANSW_CNT (0x02U)
230 #define BOARD_TPS65941_WDT_WIN1_CFG (0x03U)
231 #define BOARD_TPS65941_WDT_WIN2_CFG (0x04U)
232 #define BOARD_TPS65941_WDT_LONGWIN_CFG (0x05U)
233 #define BOARD_TPS65941_WDT_MODE_REG (0x06U)
234 #define BOARD_TPS65941_WDT_QA_CFG (0x07U)
235 #define BOARD_TPS65941_WDT_ERR_STAT (0x08U)
236 #define BOARD_TPS65941_WDT_THR_CFG (0x09U)
237 #define BOARD_TPS65941_WDT_FAIL_CNT_REG (0x0AU)
238 
240 #define BOARD_TPS65941_GPIO_SEL_SHIFT (0x05U)
241 #define BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT (0x04U)
242 #define BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT (0x03U)
243 #define BOARD_TPS65941_GPIO_PU_SEL_SHIFT (0x02U)
244 #define BOARD_TPS65941_GPIO_OD_SHIFT (0x01U)
245 #define BOARD_TPS65941_GPIO_DIR_SHIFT (0x00U)
246 
248 #define BOARD_TPS65941_NPWRON_SEL_SHIFT (0x06U)
249 #define BOARD_TPS65941_NPWRON_POL_SHIFT (0x05U)
250 #define BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT (0x03U)
251 #define BOARD_TPS65941_NPWRON_PU_SEL_SHIFT (0x02U)
252 #define BOARD_TPS65941_NPWRON_OD_SHIFT (0x00U)
253 
255 #define BOARD_TPS65941_GPIO1_IN_OUT_SHIFT (0x00U)
256 #define BOARD_TPS65941_GPIO2_IN_OUT_SHIFT (0x01U)
257 #define BOARD_TPS65941_GPIO3_IN_OUT_SHIFT (0x02U)
258 #define BOARD_TPS65941_GPIO4_IN_OUT_SHIFT (0x03U)
259 #define BOARD_TPS65941_GPIO5_IN_OUT_SHIFT (0x04U)
260 #define BOARD_TPS65941_GPIO6_IN_OUT_SHIFT (0x05U)
261 #define BOARD_TPS65941_GPIO7_IN_OUT_SHIFT (0x06U)
262 #define BOARD_TPS65941_GPIO8_IN_OUT_SHIFT (0x07U)
263 #define BOARD_TPS65941_GPIO9_IN_OUT_SHIFT (0x00U)
264 #define BOARD_TPS65941_GPIO10_IN_OUT_SHIFT (0x01U)
265 #define BOARD_TPS65941_GPIO11_IN_OUT_SHIFT (0x02U)
266 #define BOARD_TPS65941_NPWRON_IN_OUT_SHIFT (0x03U)
267 
269 #define BOARD_TPS65941_BUCK_VSEL_SHIFT (0x03U)
270 #define BOARD_TPS65941_BUCK_EN_SHIFT (0x00U)
271 #define BOARD_TPS65941_BUCK_ILIM_SHIFT (0x03U)
272 
274 #define BOARD_TPS65941_LDO_EN_SHIFT (0x00U)
275 
277 #define BOARD_TPS65941_BUCK_VSET_SHIFT (0x00U)
278 
280 #define BOARD_TPS65941_LDO_123_VSET_SHIFT (0x01U)
281 #define BOARD_TPS65941_LDO4_VSET_SHIFT (0x00U)
282 
284 #define BOARD_TPS65941_PWR_VMON_EN_SHIFT (0x04U)
285 
287 #define BOARD_TPS65941_PWR_UV_THR_SHIFT (0x03U)
288 #define BOARD_TPS65941_PWR_OV_THR_SHIFT (0x00U)
289 
291 #define BOARD_TPS65941_BUCK1_PG_SEL_SHIFT (0x00U)
292 #define BOARD_TPS65941_BUCK2_PG_SEL_SHIFT (0x02U)
293 #define BOARD_TPS65941_BUCK3_PG_SEL_SHIFT (0x04U)
294 #define BOARD_TPS65941_BUCK4_PG_SEL_SHIFT (0x06U)
295 #define BOARD_TPS65941_BUCK5_PG_SEL_SHIFT (0x00U)
296 #define BOARD_TPS65941_LDO1_PG_SEL_SHIFT (0x00U)
297 #define BOARD_TPS65941_LDO2_PG_SEL_SHIFT (0x02U)
298 #define BOARD_TPS65941_LDO3_PG_SEL_SHIFT (0x04U)
299 #define BOARD_TPS65941_LDO4_PG_SEL_SHIFT (0x06U)
300 
302 #define BOARD_TPS65941_VCCA_VMON_EN_SHIFT (0x00U)
303 #define BOARD_TPS65941_VCCA_PG_SET_SHIFT (0x06U)
304 #define BOARD_TPS65941_VCCA_UV_THR_SHIFT (0x03U)
305 #define BOARD_TPS65941_VCCA_OV_THR_SHIFT (0x00U)
306 
308 #define BOARD_TPS65941_TWARN_STAT_SHIFT (0x03U)
309 #define BOARD_TPS65941_TSD_ORD_STAT_SHIFT (0x00U)
310 #define BOARD_TPS65941_TSD_IMM_STAT_SHIFT (0x00U)
311 
313 #define BOARD_TPS65941_PGOOD_WINDOW_SHIFT (0x07U)
314 #define BOARD_TPS65941_PGOOD_POL_SHIFT (0x06U)
315 #define BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT (0x05U)
316 #define BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT (0x04U)
317 #define BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT (0x03U)
318 #define BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT (0x00U)
319 
321 #define BOARD_TPS65941_TWARN_LVL_SHIFT (0x00U)
322 
324 #define BOARD_TPS65941_ESM_START_SHIFT (0x00U)
325 #define BOARD_TPS65941_ESM_DLY1_SHIFT (0x00U)
326 #define BOARD_TPS65941_ESM_DLY2_SHIFT (0x00U)
327 #define BOARD_TPS65941_ESM_MODE_SHIFT (0x07U)
328 #define BOARD_TPS65941_ESM_EN_SHIFT (0x06U)
329 #define BOARD_TPS65941_ESM_ERR_THR_SHIFT (0x00U)
330 #define BOARD_TPS65941_ESM_HMAX_SHIFT (0x00U)
331 #define BOARD_TPS65941_ESM_HMIN_SHIFT (0x00U)
332 #define BOARD_TPS65941_ESM_LMAX_SHIFT (0x00U)
333 #define BOARD_TPS65941_ESM_LMIN_SHIFT (0x00U)
334 #define BOARD_TPS65941_ESM_ERR_CNT_SHIFT (0x00U)
335 
337 #define BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT (0x04U)
338 #define BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT (0x00U)
339 #define BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT (0x04U)
340 #define BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT (0x00U)
341 #define BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT (0x07U)
342 #define BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT (0x04U)
343 #define BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT (0x00U)
344 #define BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT (0x04U)
345 #define BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT (0x00U)
346 #define BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT (0x04U)
347 #define BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT (0x00U)
348 #define BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT (0x04U)
349 #define BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT (0x00U)
350 #define BOARD_TPS65941_RTC_WEEK_SHIFT (0x00U)
351 
353 #define BOARD_TPS65941_RTC_REG_OPT_SHIFT (0x07U)
354 #define BOARD_TPS65941_GET_TIME_SHIFT (0x06U)
355 #define BOARD_TPS65941_HOUR_MODE_SHIFT (0x03U)
356 #define BOARD_TPS65941_ROUND_30S_SHIFT (0x01U)
357 #define BOARD_TPS65941_STOP_RTC_SHIFT (0x00U)
358 
360 #define BOARD_TPS65941_ALRM_STAT_SHIFT (0x06U)
361 #define BOARD_TPS65941_TIMER_STAT_SHIFT (0x05U)
362 #define BOARD_TPS65941_RUN_SHIFT (0x01U)
363 
365 #define BOARD_TPS65941_ALARM_INTR_SHIFT (0x03U)
366 #define BOARD_TPS65941_TIMER_INTR_SHIFT (0x02U)
367 
369 #define BOARD_TPS65941_TIMER_PERIOD_SHIFT (0x00U)
370 
372 #define BOARD_TPS65941_WDT_ANSW_SHIFT (0x00U)
373 #define BOARD_TPS65941_WDT_ANSW_CNT_SHIFT (0x04U)
374 #define BOARD_TPS65941_WDT_QUES_SHIFT (0x00U)
375 #define BOARD_TPS65941_WDT_WIN1_CFG_SHIFT (0x00U)
376 #define BOARD_TPS65941_WDT_WIN2_CFG_SHIFT (0x00U)
377 #define BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT (0x00U)
378 #define BOARD_TPS65941_WDT_MODE_SHIFT (0x01U)
379 #define BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT (0x00U)
380 
382 #define BOARD_TPS65941_WDT_RST_STAT_SHIFT (0x07U)
383 #define BOARD_TPS65941_WDT_FAIL_STAT_SHIFT (0x06U)
384 #define BOARD_TPS65941_WDT_ANSW_ERR_SHIFT (0x05U)
385 #define BOARD_TPS65941_WDT_SEQ_ERR_SHIFT (0x04U)
386 #define BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT (0x03U)
387 #define BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT (0x02U)
388 #define BOARD_TPS65941_WDT_TIMEOUT_SHIFT (0x01U)
389 #define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT (0x00U)
390 
392 #define BOARD_TPS65941_WDT_RST_EN_SHIFT (0x07U)
393 #define BOARD_TPS65941_WDT_EN_SHIFT (0x06U)
394 #define BOARD_TPS65941_WDT_FAIL_THR_SHIFT (0x03U)
395 #define BOARD_TPS65941_WDT_RST_THR_SHIFT (0x00U)
396 
398 #define BOARD_TPS65941_WDT_BAD_EVT_SHIFT (0x06U)
399 #define BOARD_TPS65941_WDT_FIRST_OK_SHIFT (0x05U)
400 #define BOARD_TPS65941_WDT_FAIL_CNT_SHIFT (0x00U)
401 
403 #define BOARD_TPS65941_GPIO_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_SEL_SHIFT)
404 #define BOARD_TPS65941_GPIO_DEGLITCH_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DEGLITCH_EN_SHIFT)
405 #define BOARD_TPS65941_GPIO_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_PD_EN_SHIFT)
406 #define BOARD_TPS65941_GPIO_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_PU_SEL_SHIFT)
407 #define BOARD_TPS65941_GPIO_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_OD_SHIFT)
408 #define BOARD_TPS65941_GPIO_DIR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO_DIR_SHIFT)
409 
411 #define BOARD_TPS65941_NPWRON_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_SEL_SHIFT)
412 #define BOARD_TPS65941_NPWRON_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_POL_SHIFT)
413 #define BOARD_TPS65941_NPWRON_PU_PD_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_PD_EN_SHIFT)
414 #define BOARD_TPS65941_NPWRON_PU_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_PU_SEL_SHIFT)
415 #define BOARD_TPS65941_NPWRON_OD_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_OD_SHIFT)
416 
418 #define BOARD_TPS65941_GPIO1_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO1_IN_OUT_SHIFT)
419 #define BOARD_TPS65941_GPIO2_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO2_IN_OUT_SHIFT)
420 #define BOARD_TPS65941_GPIO3_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO3_IN_OUT_SHIFT)
421 #define BOARD_TPS65941_GPIO4_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO4_IN_OUT_SHIFT)
422 #define BOARD_TPS65941_GPIO5_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO5_IN_OUT_SHIFT)
423 #define BOARD_TPS65941_GPIO6_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO6_IN_OUT_SHIFT)
424 #define BOARD_TPS65941_GPIO7_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO7_IN_OUT_SHIFT)
425 #define BOARD_TPS65941_GPIO8_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO8_IN_OUT_SHIFT)
426 #define BOARD_TPS65941_GPIO9_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO9_IN_OUT_SHIFT)
427 #define BOARD_TPS65941_GPIO10_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO10_IN_OUT_SHIFT)
428 #define BOARD_TPS65941_GPIO11_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GPIO11_IN_OUT_SHIFT)
429 #define BOARD_TPS65941_NPWRON_IN_OUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_NPWRON_IN_OUT_SHIFT)
430 
432 #define BOARD_TPS65941_BUCK_VSEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_VSEL_SHIFT)
433 #define BOARD_TPS65941_BUCK_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_BUCK_EN_SHIFT)
434 #define BOARD_TPS65941_BUCK_ILIM_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_BUCK_ILIM_SHIFT)
435 
437 #define BOARD_TPS65941_LDO_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_LDO_EN_SHIFT)
438 
440 #define BOARD_TPS65941_BUCK_VSET_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_BUCK_VSET_SHIFT)
441 
443 #define BOARD_TPS65941_LDO_123_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO_123_VSET_SHIFT)
444 #define BOARD_TPS65941_LDO4_VSET_BIT_MASK (uint8_t)(0x3F << BOARD_TPS65941_LDO4_VSET_SHIFT)
445 
447 #define BOARD_TPS65941_PWR_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PWR_VMON_EN_SHIFT)
448 
450 #define BOARD_TPS65941_PWR_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_UV_THR_SHIFT)
451 #define BOARD_TPS65941_PWR_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_PWR_OV_THR_SHIFT)
452 
454 #define BOARD_TPS65941_BUCK1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK1_PG_SEL_SHIFT)
455 #define BOARD_TPS65941_BUCK2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK2_PG_SEL_SHIFT)
456 #define BOARD_TPS65941_BUCK3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK3_PG_SEL_SHIFT)
457 #define BOARD_TPS65941_BUCK4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK4_PG_SEL_SHIFT)
458 #define BOARD_TPS65941_BUCK5_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_BUCK5_PG_SEL_SHIFT)
459 #define BOARD_TPS65941_LDO1_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO1_PG_SEL_SHIFT)
460 #define BOARD_TPS65941_LDO2_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO2_PG_SEL_SHIFT)
461 #define BOARD_TPS65941_LDO3_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO3_PG_SEL_SHIFT)
462 #define BOARD_TPS65941_LDO4_PG_SEL_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_LDO4_PG_SEL_SHIFT)
463 
465 #define BOARD_TPS65941_VCCA_VMON_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_VMON_EN_SHIFT)
466 #define BOARD_TPS65941_VCCA_PG_SET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_VCCA_PG_SET_SHIFT)
467 #define BOARD_TPS65941_VCCA_UV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_UV_THR_SHIFT)
468 #define BOARD_TPS65941_VCCA_OV_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_VCCA_OV_THR_SHIFT)
469 
471 #define BOARD_TPS65941_TWARN_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_STAT_SHIFT)
472 #define BOARD_TPS65941_TSD_ORD_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_ORD_STAT_SHIFT)
473 #define BOARD_TPS65941_TSD_IMM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TSD_IMM_STAT_SHIFT)
474 
476 #define BOARD_TPS65941_PGOOD_WINDOW_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_WINDOW_SHIFT)
477 #define BOARD_TPS65941_PGOOD_POL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_POL_SHIFT)
478 #define BOARD_TPS65941_PGOOD_NRSTOUT_SOC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SOC_SHIFT)
479 #define BOARD_TPS65941_PGOOD_NRSTOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_NRSTOUT_SHIFT)
480 #define BOARD_TPS65941_PGOOD_TDIE_WARN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_TDIE_WARN_SHIFT)
481 #define BOARD_TPS65941_PGOOD_VCCA_SEL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_PGOOD_VCCA_SEL_SHIFT)
482 
484 #define BOARD_TPS65941_TWARN_LVL_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TWARN_LVL_SHIFT)
485 
487 #define BOARD_TPS65941_ESM_START_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_START_SHIFT)
488 #define BOARD_TPS65941_ESM_DLY1_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY1_SHIFT)
489 #define BOARD_TPS65941_ESM_DLY2_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_DLY2_SHIFT)
490 #define BOARD_TPS65941_ESM_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_MODE_SHIFT)
491 #define BOARD_TPS65941_ESM_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ESM_EN_SHIFT)
492 #define BOARD_TPS65941_ESM_ERR_THR_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_ESM_ERR_THR_SHIFT)
493 #define BOARD_TPS65941_ESM_HMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMAX_SHIFT)
494 #define BOARD_TPS65941_ESM_HMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_HMIN_SHIFT)
495 #define BOARD_TPS65941_ESM_LMAX_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMAX_SHIFT)
496 #define BOARD_TPS65941_ESM_LMIN_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_ESM_LMIN_SHIFT)
497 #define BOARD_TPS65941_ESM_ERR_CNT_BIT_MASK (uint8_t)(0x1F << BOARD_TPS65941_ESM_ERR_CNT_SHIFT)
498 
500 #define BOARD_TPS65941_RTC_ALRM_SEC_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_SEC_1_SHIFT)
501 #define BOARD_TPS65941_RTC_ALRM_SEC_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_SEC_0_SHIFT)
502 #define BOARD_TPS65941_RTC_ALRM_MIN_1_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_ALRM_MIN_1_SHIFT)
503 #define BOARD_TPS65941_RTC_ALRM_MIN_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MIN_0_SHIFT)
504 #define BOARD_TPS65941_RTC_ALRM_AM_PM_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_AM_PM_SHIFT)
505 #define BOARD_TPS65941_RTC_ALRM_HR_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_HR_1_SHIFT)
506 #define BOARD_TPS65941_RTC_ALRM_HR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_HR_0_SHIFT)
507 #define BOARD_TPS65941_RTC_ALRM_DAY_1_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_RTC_ALRM_DAY_1_SHIFT)
508 #define BOARD_TPS65941_RTC_ALRM_DAY_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_DAY_0_SHIFT)
509 #define BOARD_TPS65941_RTC_ALRM_MON_1_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_ALRM_MON_1_SHIFT)
510 #define BOARD_TPS65941_RTC_ALRM_MON_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_MON_0_SHIFT)
511 #define BOARD_TPS65941_RTC_ALRM_YR_1_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_1_SHIFT)
512 #define BOARD_TPS65941_RTC_ALRM_YR_0_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_RTC_ALRM_YR_0_SHIFT)
513 #define BOARD_TPS65941_RTC_WEEK_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_RTC_WEEK_SHIFT)
514 
516 #define BOARD_TPS65941_RTC_REG_OPT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RTC_REG_OPT_SHIFT)
517 #define BOARD_TPS65941_GET_TIME_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_GET_TIME_SHIFT)
518 #define BOARD_TPS65941_HOUR_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_HOUR_MODE_SHIFT)
519 #define BOARD_TPS65941_ROUND_30S_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ROUND_30S_SHIFT)
520 #define BOARD_TPS65941_STOP_RTC_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_STOP_RTC_SHIFT)
521 
523 #define BOARD_TPS65941_ALRM_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALRM_STAT_SHIFT)
524 #define BOARD_TPS65941_TIMER_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_STAT_SHIFT)
525 #define BOARD_TPS65941_RUN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_RUN_SHIFT)
526 
528 #define BOARD_TPS65941_ALARM_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_ALARM_INTR_SHIFT)
529 #define BOARD_TPS65941_TIMER_INTR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_TIMER_INTR_SHIFT)
530 
532 #define BOARD_TPS65941_TIMER_PERIOD_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_TIMER_PERIOD_SHIFT)
533 
535 #define BOARD_TPS65941_WDT_ANSW_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_ANSW_SHIFT)
536 #define BOARD_TPS65941_WDT_ANSW_CNT_BIT_MASK (uint8_t)(0x03 << BOARD_TPS65941_WDT_ANSW_CNT_SHIFT)
537 #define BOARD_TPS65941_WDT_QUES_BIT_MASK (uint8_t)(0x0F << BOARD_TPS65941_WDT_QUES_SHIFT)
538 #define BOARD_TPS65941_WDT_WIN1_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN1_CFG_SHIFT)
539 #define BOARD_TPS65941_WDT_WIN2_CFG_BIT_MASK (uint8_t)(0x7F << BOARD_TPS65941_WDT_WIN2_CFG_SHIFT)
540 #define BOARD_TPS65941_WDT_LONGWIN_CFG_BIT_MASK (uint8_t)(0xFF << BOARD_TPS65941_WDT_LONGWIN_CFG_SHIFT)
541 #define BOARD_TPS65941_WDT_MODE_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_MODE_SHIFT)
542 #define BOARD_TPS65941_WDT_LONGWIN_RET_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LONGWIN_RET_SHIFT)
543 
545 #define BOARD_TPS65941_WDT_RST_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_STAT_SHIFT)
546 #define BOARD_TPS65941_WDT_FAIL_STAT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_STAT_SHIFT)
547 #define BOARD_TPS65941_WDT_ANSW_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERR_SHIFT)
548 #define BOARD_TPS65941_WDT_SEQ_ERR_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_SEQ_ERR_SHIFT)
549 #define BOARD_TPS65941_WDT_ANSW_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_ANSW_ERLY_SHIFT)
550 #define BOARD_TPS65941_WDT_TRIG_ERLY_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TRIG_ERLY_SHIFT)
551 #define BOARD_TPS65941_WDT_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_TIMEOUT_SHIFT)
552 #define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_SHIFT)
553 
555 #define BOARD_TPS65941_WDT_RST_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_RST_EN_SHIFT)
556 #define BOARD_TPS65941_WDT_EN_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_EN_SHIFT)
557 #define BOARD_TPS65941_WDT_FAIL_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_FAIL_THR_SHIFT)
558 #define BOARD_TPS65941_WDT_RST_THR_BIT_MASK (uint8_t)(0x07 << BOARD_TPS65941_WDT_RST_THR_SHIFT)
559 
561 #define BOARD_TPS65941_WDT_BAD_EVT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_BAD_EVT_SHIFT)
562 #define BOARD_TPS65941_WDT_FIRST_OK_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FIRST_OK_SHIFT)
563 #define BOARD_TPS65941_WDT_FAIL_CNT_BIT_MASK (uint8_t)(0x01 << BOARD_TPS65941_WDT_FAIL_CNT_SHIFT)
564 
566 #define BOARD_TPS65941_DISABLE (0U)
567 #define BOARD_TPS65941_ENABLE (1U)
568 
570 #define BOARD_TPS65941_PULLUP_DOWN (0U)
571 #define BOARD_TPS65941_OPEN_DRAIN (1U)
572 
574 #define BOARD_TPS65941_GPIO_LOW (0U)
575 #define BOARD_TPS65941_GPIO_HIGH (1U)
576 
578 #define BOARD_TPS65941_GPIO_DIR_IN (0U)
579 #define BOARD_TPS65941_GPIO_DIR_OUT (1U)
580 
581 #define BOARD_TPS65941_GPIO_MODE (0x0U)
582 #define BOARD_TPS65941_GPIO_PIN_MAX (11U)
583 #define BOARD_TPS65941_NPWRON_PIN (0)
584 
586 #define BOARD_TPS65941_BUCK1_RESOURCE (0U)
587 #define BOARD_TPS65941_BUCK2_RESOURCE (1U)
588 #define BOARD_TPS65941_BUCK3_RESOURCE (2U)
589 #define BOARD_TPS65941_BUCK4_RESOURCE (3U)
590 #define BOARD_TPS65941_BUCK5_RESOURCE (4U)
591 #define BOARD_TPS65941_LDO1_RESOURCE (5U)
592 #define BOARD_TPS65941_LDO2_RESOURCE (6U)
593 #define BOARD_TPS65941_LDO3_RESOURCE (7U)
594 #define BOARD_TPS65941_LDO4_RESOURCE (8U)
595 
597 #define BOARD_TPS65941_INTR_TYPE_BUCK_ERR (0U)
598 #define BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR (1U)
599 #define BOARD_TPS65941_INTR_TYPE_SEVERE_ERR (2U)
600 #define BOARD_TPS65941_INTR_TYPE_MODERATE_ERR (3U)
601 #define BOARD_TPS65941_INTR_TYPE_MISC_WARN (4U)
602 #define BOARD_TPS65941_INTR_TYPE_STARTUP_SRC (5U)
603 #define BOARD_TPS65941_INTR_TYPE_GPIO (6U)
604 #define BOARD_TPS65941_INTR_TYPE_FSM_ERR (7U)
605 
607 /* Upper 8-bit indicates the interrupt type and lower 8-bits are interrupt
608  number mapped based on the register offsets */
609 #define BOARD_TPS65941_INTR_ID_BUCK1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x00U)
610 #define BOARD_TPS65941_INTR_ID_BUCK1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x01U)
611 #define BOARD_TPS65941_INTR_ID_BUCK1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x02U)
612 #define BOARD_TPS65941_INTR_ID_BUCK1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x03U)
613 #define BOARD_TPS65941_INTR_ID_BUCK2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x04U)
614 #define BOARD_TPS65941_INTR_ID_BUCK2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x05U)
615 #define BOARD_TPS65941_INTR_ID_BUCK2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x06U)
616 #define BOARD_TPS65941_INTR_ID_BUCK2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x07U)
617 #define BOARD_TPS65941_INTR_ID_BUCK3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x08U)
618 #define BOARD_TPS65941_INTR_ID_BUCK3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x09U)
619 #define BOARD_TPS65941_INTR_ID_BUCK3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x0AU)
620 #define BOARD_TPS65941_INTR_ID_BUCK3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0BU)
621 #define BOARD_TPS65941_INTR_ID_BUCK4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0CU)
622 #define BOARD_TPS65941_INTR_ID_BUCK4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0DU)
623 #define BOARD_TPS65941_INTR_ID_BUCK4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x0EU)
624 #define BOARD_TPS65941_INTR_ID_BUCK4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x0FU)
625 #define BOARD_TPS65941_INTR_ID_BUCK5_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x10U)
626 #define BOARD_TPS65941_INTR_ID_BUCK5_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x11U)
627 #define BOARD_TPS65941_INTR_ID_BUCK5_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (1 << 8) | 0x12U)
628 #define BOARD_TPS65941_INTR_ID_BUCK5_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_BUCK_ERR) << 16) | (0 << 8) | 0x13U)
629 
630 #define BOARD_TPS65941_INTR_ID_LDO1_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x00U)
631 #define BOARD_TPS65941_INTR_ID_LDO1_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x01U)
632 #define BOARD_TPS65941_INTR_ID_LDO1_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x02U)
633 #define BOARD_TPS65941_INTR_ID_LDO1_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x03U)
634 #define BOARD_TPS65941_INTR_ID_LDO2_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x04U)
635 #define BOARD_TPS65941_INTR_ID_LDO2_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x05U)
636 #define BOARD_TPS65941_INTR_ID_LDO2_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x06U)
637 #define BOARD_TPS65941_INTR_ID_LDO2_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x07U)
638 #define BOARD_TPS65941_INTR_ID_LDO3_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x08U)
639 #define BOARD_TPS65941_INTR_ID_LDO3_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x09U)
640 #define BOARD_TPS65941_INTR_ID_LDO3_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x0AU)
641 #define BOARD_TPS65941_INTR_ID_LDO3_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0BU)
642 #define BOARD_TPS65941_INTR_ID_LDO4_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0CU)
643 #define BOARD_TPS65941_INTR_ID_LDO4_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0DU)
644 #define BOARD_TPS65941_INTR_ID_LDO4_SC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (1 << 8) | 0x0EU)
645 #define BOARD_TPS65941_INTR_ID_LDO4_ILIM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x0FU)
646 #define BOARD_TPS65941_INTR_ID_VCCA_OV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x10U)
647 #define BOARD_TPS65941_INTR_ID_VCCA_UV ((((uint32_t)BOARD_TPS65941_INTR_TYPE_LDO_VMON_ERR) << 16) | (0 << 8) | 0x11U)
648 
649 #define BOARD_TPS65941_INTR_ID_GPIO1_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x00U)
650 #define BOARD_TPS65941_INTR_ID_GPIO2_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x01U)
651 #define BOARD_TPS65941_INTR_ID_GPIO3_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x02U)
652 #define BOARD_TPS65941_INTR_ID_GPIO4_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x03U)
653 #define BOARD_TPS65941_INTR_ID_GPIO5_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x04U)
654 #define BOARD_TPS65941_INTR_ID_GPIO6_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x05U)
655 #define BOARD_TPS65941_INTR_ID_GPIO7_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x06U)
656 #define BOARD_TPS65941_INTR_ID_GPIO8_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x07U)
657 #define BOARD_TPS65941_INTR_ID_GPIO9_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x10U)
658 #define BOARD_TPS65941_INTR_ID_GPIO10_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x11U)
659 #define BOARD_TPS65941_INTR_ID_GPIO11_FALL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x12U)
660 
661 #define BOARD_TPS65941_INTR_ID_GPIO1_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x08U)
662 #define BOARD_TPS65941_INTR_ID_GPIO2_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x09U)
663 #define BOARD_TPS65941_INTR_ID_GPIO3_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0AU)
664 #define BOARD_TPS65941_INTR_ID_GPIO4_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0BU)
665 #define BOARD_TPS65941_INTR_ID_GPIO5_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0CU)
666 #define BOARD_TPS65941_INTR_ID_GPIO6_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0DU)
667 #define BOARD_TPS65941_INTR_ID_GPIO7_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0EU)
668 #define BOARD_TPS65941_INTR_ID_GPIO8_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x0FU)
669 #define BOARD_TPS65941_INTR_ID_GPIO9_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x13U)
670 #define BOARD_TPS65941_INTR_ID_GPIO10_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x14U)
671 #define BOARD_TPS65941_INTR_ID_GPIO11_RISE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_GPIO) << 16) | (0 << 8) | 0x15U)
672 
673 #define BOARD_TPS65941_INTR_ID_FSD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x04U)
674 #define BOARD_TPS65941_INTR_ID_RTC ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (1 << 8) | 0x02U)
675 #define BOARD_TPS65941_INTR_ID_ENABLE ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x01U)
676 #define BOARD_TPS65941_INTR_ID_NPWRON_START ((((uint32_t)BOARD_TPS65941_INTR_TYPE_STARTUP_SRC) << 16) | (0 << 8) | 0x00U)
677 
678 #define BOARD_TPS65941_INTR_ID_TWARN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x03U)
679 #define BOARD_TPS65941_INTR_ID_EXT_CLK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x01U)
680 #define BOARD_TPS65941_INTR_ID_BIST_PASS ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MISC_WARN) << 16) | (0 << 8) | 0x00U)
681 
682 #define BOARD_TPS65941_INTR_ID_RECOV_CNT ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (1 << 8) | 0x06U)
683 #define BOARD_TPS65941_INTR_ID_NPWRON_LONG ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x05U)
684 #define BOARD_TPS65941_INTR_ID_SPMI_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x04U)
685 #define BOARD_TPS65941_INTR_ID_PFSM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x03U)
686 #define BOARD_TPS65941_INTR_ID_REG_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x02U)
687 #define BOARD_TPS65941_INTR_ID_BIST_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (0 << 8) | 0x01U)
688 #define BOARD_TPS65941_INTR_ID_TSD_ORD ((((uint32_t)BOARD_TPS65941_INTR_TYPE_MODERATE_ERR) << 16) | (1 << 8) | 0x00U)
689 
690 #define BOARD_TPS65941_INTR_ID_VCCA_OVP ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) | (1 << 8) | 0x01U)
691 #define BOARD_TPS65941_INTR_ID_TSD_IMM ((((uint32_t)BOARD_TPS65941_INTR_TYPE_SEVERE_ERR) << 16) | (1 << 8) | 0x00U)
692 
693 #define BOARD_TPS65941_INTR_ID_IMM_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x00U)
694 #define BOARD_TPS65941_INTR_ID_ORD_SHUTDOWN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x01U)
695 #define BOARD_TPS65941_INTR_ID_MCU_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x02U)
696 #define BOARD_TPS65941_INTR_ID_SOC_PWR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x03U)
697 #define BOARD_TPS65941_INTR_ID_COMM_FRM_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x08U)
698 #define BOARD_TPS65941_INTR_ID_COMM_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x09U)
699 #define BOARD_TPS65941_INTR_ID_COMM_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0BU)
700 #define BOARD_TPS65941_INTR_ID_I2C2_CRC_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0DU)
701 #define BOARD_TPS65941_INTR_ID_I2C2_ADR_ERR ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x0FU)
702 #define BOARD_TPS65941_INTR_ID_EN_DRV_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x10U)
703 #define BOARD_TPS65941_INTR_ID_NINT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x11U)
704 #define BOARD_TPS65941_INTR_ID_NRSTOUT_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x12U)
705 #define BOARD_TPS65941_INTR_ID_NRSTOUT_SOC_RDBACK ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x13U)
706 #define BOARD_TPS65941_INTR_ID_ESM_SOC_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x18U)
707 #define BOARD_TPS65941_INTR_ID_ESM_SOC_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x19U)
708 #define BOARD_TPS65941_INTR_ID_ESM_SOC_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1AU)
709 #define BOARD_TPS65941_INTR_ID_ESM_MCU_PIN ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1BU)
710 #define BOARD_TPS65941_INTR_ID_ESM_MCU_FAIL ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1CU)
711 #define BOARD_TPS65941_INTR_ID_ESM_MCU_RST ((((uint32_t)BOARD_TPS65941_INTR_TYPE_FSM_ERR) << 16) | (0 << 8) | 0x1DU)
712 
713 #define BOARD_TPS65941_INTR_REG_WIDTH (0x8U)
714 
716 #define BOARD_TPS65941_INTR_ENABLE (0)
717 #define BOARD_TPS65941_INTR_DISABLE (1)
718 
720 #define BOARD_TPS65941_INTR_SET (1)
721 #define BOARD_TPS65941_INTR_UNSET (0)
722 
724 #define BOARD_TPS65941_PG_3V3_LEVEL (0)
725 #define BOARD_TPS65941_PG_5V_LEVEL (1)
726 
728 #define BOARD_TPS65941_PG_THR_3_PERCENT (0x0U)
729 #define BOARD_TPS65941_PG_THR_3_5_PERCENT (0x1U)
730 #define BOARD_TPS65941_PG_THR_4_PERCENT (0x2U)
731 #define BOARD_TPS65941_PG_THR_5_PERCENT (0x3U)
732 #define BOARD_TPS65941_PG_THR_6_PERCENT (0x4U)
733 #define BOARD_TPS65941_PG_THR_7_PERCENT (0x5U)
734 #define BOARD_TPS65941_PG_THR_8_PERCENT (0x6U)
735 #define BOARD_TPS65941_PG_THR_10_PERCENT (0x7U)
736 
738 #define BOARD_TPS65941_ILIM_2_5A (0x2U)
739 #define BOARD_TPS65941_ILIM_3_5A (0x3U)
740 #define BOARD_TPS65941_ILIM_4_5A (0x4U)
741 #define BOARD_TPS65941_ILIM_5_5A (0x5U)
742 
744 #define BOARD_TPS65941_OV_UV_DISABLE (0)
745 #define BOARD_TPS65941_OV_UV_ENABLE (1)
746 
748 #define BOARD_TPS65941_PGOOD_MASK (0U)
749 #define BOARD_TPS65941_PGOOD_UNMASK (1U)
750 
752 #define BOARD_TPS65941_UV_MONITOR (0U)
753 #define BOARD_TPS65941_UV_OV_MONITOR (1U)
754 
756 #define BOARD_TPS65941_TDIE_NO_WARN (0)
757 #define BOARD_TPS65941_TDIE_WARN (1)
758 #define BOARD_TPS65941_TDIE_WARN_ORD_SD (2)
759 #define BOARD_TPS65941_TDIE_WARN_IMM_SD (3)
760 
762 #define BOARD_TPS65941_THERMAL_TEMP_120C (0x0U)
763 #define BOARD_TPS65941_THERMAL_TEMP_130C (0x1U)
764 
766 #define BOARD_TPS65941_ESM_STOP (0x0)
767 #define BOARD_TPS65941_ESM_START (0x1)
768 
770 #define BOARD_TPS65941_ESM_DISABLE (0x0)
771 #define BOARD_TPS65941_ESM_ENABLE (0x1)
772 
774 #define BOARD_TPS65941_SECOND_INTR_PERIOD (0x0U)
775 #define BOARD_TPS65941_MINUTE_INTR_PERIOD (0x1U)
776 #define BOARD_TPS65941_HOUR_INTR_PERIOD (0x2U)
777 #define BOARD_TPS65941_DAY_INTR_PERIOD (0x3U)
778 
780 #define BOARD_TPS65941_ALARM_INTR_ENABLE (0x1U)
781 #define BOARD_TPS65941_ALARM_INTR_DISABLE (0x0U)
782 #define BOARD_TPS65941_TIMER_INTR_ENABLE (0x1U)
783 #define BOARD_TPS65941_TIMER_INTR_DISABLE (0x0U)
784 
786 #define BOARD_TPS65941_WDT_DISABLE (0x1U)
787 #define BOARD_TPS65941_WDT_ENABLE (0x0U)
788 
790 #define BOARD_TPS65941_WDT_TRIGGER_MODE (0x0U)
791 #define BOARD_TPS65941_WDT_QA_MODE (0x1U)
792 
794 #define BOARD_TPS65941_WDT_RST_DISABLE (0x0U)
795 #define BOARD_TPS65941_WDT_RST_ENABLE (0x1U)
796 
798 #define BOARD_TPS65941_ESM_SOC (0x0U)
799 #define BOARD_TPS65941_ESM_MCU (0x1U)
800 
802 #define BOARD_TPS65941_ESM_LEVEL_MODE (0x0U)
803 #define BOARD_TPS65941_ESM_PWM_MODE (0x1U)
804 
806 #define BOARD_TPS65941_12_HOUR_MODE (1)
807 #define BOARD_TPS65941_24_HOUR_MODE (0)
808 
810 #define BOARD_TPS65941_AM_MODE (0)
811 #define BOARD_TPS65941_PM_MODE (1)
812 
814 #define BOARD_TPS65941_SUNDAY (0)
815 #define BOARD_TPS65941_MONDAY (1)
816 #define BOARD_TPS65941_TUESDAY (2)
817 #define BOARD_TPS65941_WEDNESDAY (3)
818 #define BOARD_TPS65941_THURSDAY (4)
819 #define BOARD_TPS65941_FRIDAY (5)
820 #define BOARD_TPS65941_SATURDAY (6)
821 
823 #define BOARD_TPS65941_RTC_FROZEN (0)
824 #define BOARD_TPS65941_RTC_START (1)
825 
827 #define BOARD_TPS65941_WDT_RST_INT (0)
828 #define BOARD_TPS65941_WDT_FAIL_INT (1)
829 #define BOARD_TPS65941_WDT_ANSW_ERR (2)
830 #define BOARD_TPS65941_WDT_SEQ_ERR (3)
831 #define BOARD_TPS65941_WDT_ANSW_ERLY_ERR (4)
832 #define BOARD_TPS65941_WDT_TRIG_ERLY_ERR (5)
833 #define BOARD_TPS65941_WDT_TIMEOUT_ERR (6)
834 #define BOARD_TPS65941_WDT_LNGWIN_TIMEOUT_ERR (7)
835 #define BOARD_TPS65941_WDT_ERR_LATCHED (1)
836 #define BOARD_TPS65941_WDT_NO_ERR (0)
837 
839 #define BOARD_I2C_NUM_OF_BYTES_01 (1U)
840 
841 /* @} */
842 
858 typedef struct Board_Tps65941GpioRegCfg_s
859 {
860  uint8_t regAddr;
862  uint8_t outRegAddr;
864  uint8_t inRegAddr;
866  uint8_t inOutRegBitPos;
868 }Board_Tps65941GpioRegCfg;
869 
873 typedef struct Board_Tps65941PwrResourceRegCfg_s
874 {
875  uint8_t cntrRegAddr;
877  uint8_t cfgRegAddr;
879  uint8_t voltageRegAddr;
881  uint8_t pgRegAddr;
883 }Board_Tps65941PwrResourceRegCfg;
884 
888 typedef struct Board_Tps65941IntrRegMap_s
889 {
890  uint8_t maskRegAddr;
892  uint8_t intrRegAddr;
894  uint8_t maxReg;
896 }Board_Tps65941IntrRegMap;
897 
901 typedef struct Board_Tps65941VoltMonitorCfg_s
902 {
903  uint8_t monitortype;
905  uint8_t regularEnable;
907  uint8_t currentLimit;
909  uint8_t voltOverLimit;
911  uint8_t voltUnderLimit;
913  uint8_t pgoodEnable;
915  uint8_t overVoltEnable;
917 }Board_Tps65941VoltMonitorCfg;
918 
922 typedef struct Board_Tps65941RtcTime_s
923 {
924  uint8_t seconds;
926  uint8_t minutes;
928  uint8_t hour;
930  uint8_t timeMode;
933  uint8_t meridienMode;
935 }Board_Tps65941RtcTime;
936 
940 typedef struct Board_Tps65941RtcDate_s
941 {
942  uint8_t date;
944  uint8_t month;
946  uint8_t year;
948  uint8_t week;
950 }Board_Tps65941RtcDate;
951 
955 typedef struct Board_Tps65941WdtCfg_s
956 {
957  uint8_t longWinDuration;
959  uint8_t win1Duration;
961  uint8_t win2Duration;
963  uint8_t failThreshold;
965  uint8_t rstThreshold;
967  uint8_t rstEnable;
969 }Board_Tps65941WdtCfg;
970 
974 typedef struct Board_Tps65941EsmCfg_s
975 {
976  uint8_t delay1TimeInterval;
978  uint8_t delay2TimeInterval;
980  uint8_t maxHPTimeThreshold;
982  uint8_t minHPTimeThreshold;
984  uint8_t maxLPTimeThreshold;
986  uint8_t minLPTimeThreshold;
988 }Board_Tps65941EsmCfg;
989 
1003 Board_STATUS Board_tps65941GpioRead(void *handle,
1004  uint8_t slaveAddr,
1005  uint8_t pinNum,
1006  uint8_t *pinValue);
1007 
1023 Board_STATUS Board_tps65941GpioWrite(void *handle,
1024  uint8_t slaveAddr,
1025  uint8_t pinNum,
1026  uint8_t pinValue);
1027 
1050 Board_STATUS Board_tps65941SetVoltage(void *handle,
1051  uint8_t slaveAddr,
1052  uint8_t powerResource,
1053  uint16_t millivolt);
1054 
1077 Board_STATUS Board_tps65941GetVoltage(void *handle,
1078  uint8_t slaveAddr,
1079  uint8_t powerResource,
1080  uint16_t *millivolt);
1081 
1103 Board_STATUS Board_tps65941ConvertVolt(uint8_t voutCode,
1104  uint8_t powerResource,
1105  uint16_t *millivolt);
1106 
1128 Board_STATUS Board_tps65941ConvertVoutCode(uint16_t millivolt,
1129  uint8_t powerResource,
1130  uint8_t *voutCode);
1131 
1147 Board_STATUS Board_tps65941ConfigIntr(void *handle,
1148  uint8_t slaveAddr,
1149  uint32_t intrID,
1150  uint8_t intrEnable);
1151 
1168 Board_STATUS Board_tps65941GetIntrStatus(void *handle,
1169  uint8_t slaveAddr,
1170  uint32_t intrID,
1171  uint8_t *intrStatus);
1172 
1184 Board_STATUS Board_tps65941ClearIntr(void *handle,
1185  uint8_t slaveAddr,
1186  uint32_t intrID);
1187 
1202 Board_STATUS Board_tps65941SetThermalThresVal(void *handle,
1203  uint8_t slaveAddr,
1204  uint32_t thermalThresholdVal);
1205 
1222 Board_STATUS Board_tps65941GetThermalStatus(void *handle,
1223  uint8_t slaveAddr,
1224  uint32_t *thermalStatus);
1225 
1237 Board_STATUS Board_tps65941SetThermalMonitor(void *handle,
1238  uint8_t slaveAddr);
1239 
1262 Board_STATUS Board_tps65941SetVoltageMonitor(void *handle,
1263  uint8_t slaveAddr,
1264  uint8_t powerResource,
1265  Board_Tps65941VoltMonitorCfg *voltMonCfg);
1266 
1283 Board_STATUS Board_tps65941SetVccaMonitor(void *handle,
1284  uint8_t slaveAddr,
1285  uint8_t vccaPgLevel,
1286  Board_Tps65941VoltMonitorCfg *voltMonitorCfg);
1287 
1301 Board_STATUS Board_tps65941SetRtc(void *handle,
1302  uint8_t slaveAddr,
1303  Board_Tps65941RtcTime *timeCfg,
1304  Board_Tps65941RtcDate *dateCfg);
1305 
1319 Board_STATUS Board_tps65941GetRtc(void *handle,
1320  uint8_t slaveAddr,
1321  Board_Tps65941RtcTime *timeCfg,
1322  Board_Tps65941RtcDate *dateCfg);
1323 
1337 Board_STATUS Board_tps65941SetAlarmIntr(void *handle,
1338  uint8_t slaveAddr,
1339  Board_Tps65941RtcTime *timeCfg,
1340  Board_Tps65941RtcDate *dateCfg);
1341 
1359 Board_STATUS Board_tps65941SetTimerIntr(void *handle,
1360  uint8_t slaveAddr,
1361  uint8_t timerPeriod);
1362 
1378 Board_STATUS Board_tps65941WdtDisable(void *handle,
1379  uint8_t slaveAddr,
1380  uint8_t wdtDisable);
1381 
1398 Board_STATUS Board_tps65941WdtConfig(void *handle,
1399  uint8_t slaveAddr,
1400  uint8_t wdtCfgMode,
1401  Board_Tps65941WdtCfg *wdtCfg);
1402 
1427 Board_STATUS Board_tps65941GetWdtStat(void *handle,
1428  uint8_t slaveAddr,
1429  uint8_t wdtErrType,
1430  uint8_t *wdtErrStat);
1431 
1451 Board_STATUS Board_tps65941StartEsm(void *handle,
1452  uint8_t slaveAddr,
1453  uint8_t esmCfg,
1454  uint8_t esmMode);
1455 
1470 Board_STATUS Board_tps65941StopEsm(void *handle,
1471  uint8_t slaveAddr,
1472  uint8_t esmCfg);
1473 
1489 Board_STATUS Board_tps65941ConfigEsm(void *handle,
1490  uint8_t slaveAddr,
1491  uint8_t esmCfgType,
1492  Board_Tps65941EsmCfg *esmCfg);
1493 
1510 Board_STATUS Board_tps65941GetEsmCount(void *handle,
1511  uint8_t slaveAddr,
1512  uint8_t esmCfg,
1513  uint8_t *esmErrCnt);
1514 
1515 #ifdef __cplusplus
1516 }
1517 #endif /* __cplusplus */
1518 
1519 #endif /* _TPS65941_H_ */
1520 
1521 /* @} */
1522 
1523 /* Nothing past this point */
Board_tps65941ConfigEsm
Board_STATUS Board_tps65941ConfigEsm(void *handle, uint8_t slaveAddr, uint8_t esmCfgType, Board_Tps65941EsmCfg *esmCfg)
TPS65941 ESM configuration function.
Board_Tps65941GpioRegCfg::outRegAddr
uint8_t outRegAddr
Definition: tps65941.h:862
Board_Tps65941VoltMonitorCfg::voltUnderLimit
uint8_t voltUnderLimit
Definition: tps65941.h:911
Board_tps65941StopEsm
Board_STATUS Board_tps65941StopEsm(void *handle, uint8_t slaveAddr, uint8_t esmCfg)
Stop TPS65941 ESM function.
Board_Tps65941EsmCfg::maxHPTimeThreshold
uint8_t maxHPTimeThreshold
Definition: tps65941.h:980
Board_tps65941SetVoltage
Board_STATUS Board_tps65941SetVoltage(void *handle, uint8_t slaveAddr, uint8_t powerResource, uint16_t millivolt)
TPS65941 set voltage function.
Board_Tps65941RtcTime::timeMode
uint8_t timeMode
Definition: tps65941.h:930
Board_Tps65941RtcTime::hour
uint8_t hour
Definition: tps65941.h:928
Board_Tps65941IntrRegMap
TPS65941 power resource details object structure.
Definition: tps65941.h:888
Board_tps65941GetEsmCount
Board_STATUS Board_tps65941GetEsmCount(void *handle, uint8_t slaveAddr, uint8_t esmCfg, uint8_t *esmErrCnt)
Get the ESM error count function.
Board_Tps65941VoltMonitorCfg
TPS65941 voltage monitoring details object structure.
Definition: tps65941.h:901
Board_tps65941SetRtc
Board_STATUS Board_tps65941SetRtc(void *handle, uint8_t slaveAddr, Board_Tps65941RtcTime *timeCfg, Board_Tps65941RtcDate *dateCfg)
Set the TPS65941 RTC date and time function.
Board_Tps65941RtcDate::year
uint8_t year
Definition: tps65941.h:946
Board_tps65941GetRtc
Board_STATUS Board_tps65941GetRtc(void *handle, uint8_t slaveAddr, Board_Tps65941RtcTime *timeCfg, Board_Tps65941RtcDate *dateCfg)
Get the TPS65941 RTC date and time function.
Board_Tps65941EsmCfg::delay1TimeInterval
uint8_t delay1TimeInterval
Definition: tps65941.h:976
Board_tps65941SetVccaMonitor
Board_STATUS Board_tps65941SetVccaMonitor(void *handle, uint8_t slaveAddr, uint8_t vccaPgLevel, Board_Tps65941VoltMonitorCfg *voltMonitorCfg)
Set the Vcca voltage monitoring function.
Board_tps65941GetVoltage
Board_STATUS Board_tps65941GetVoltage(void *handle, uint8_t slaveAddr, uint8_t powerResource, uint16_t *millivolt)
TPS65941 read voltage function.
I2C.h
I2C driver interface.
Board_Tps65941GpioRegCfg::regAddr
uint8_t regAddr
Definition: tps65941.h:860
Board_Tps65941WdtCfg::rstThreshold
uint8_t rstThreshold
Definition: tps65941.h:965
Board_Tps65941GpioRegCfg::inRegAddr
uint8_t inRegAddr
Definition: tps65941.h:864
Board_Tps65941VoltMonitorCfg::monitortype
uint8_t monitortype
Definition: tps65941.h:903
Board_Tps65941RtcDate
TPS65941 RTC Date object structure.
Definition: tps65941.h:940
Board_Tps65941EsmCfg
TPS65941 ESM configuration parameters object structure.
Definition: tps65941.h:974
Board_tps65941GetWdtStat
Board_STATUS Board_tps65941GetWdtStat(void *handle, uint8_t slaveAddr, uint8_t wdtErrType, uint8_t *wdtErrStat)
TPS65941 watchdog error status function.
Board_Tps65941PwrResourceRegCfg::pgRegAddr
uint8_t pgRegAddr
Definition: tps65941.h:881
Board_tps65941SetAlarmIntr
Board_STATUS Board_tps65941SetAlarmIntr(void *handle, uint8_t slaveAddr, Board_Tps65941RtcTime *timeCfg, Board_Tps65941RtcDate *dateCfg)
Set the alarm interrupt in TPS65941 RTC function.
Board_Tps65941GpioRegCfg::inOutRegBitPos
uint8_t inOutRegBitPos
Definition: tps65941.h:866
Board_Tps65941WdtCfg::longWinDuration
uint8_t longWinDuration
Definition: tps65941.h:957
Board_Tps65941WdtCfg::win1Duration
uint8_t win1Duration
Definition: tps65941.h:959
Board_tps65941ClearIntr
Board_STATUS Board_tps65941ClearIntr(void *handle, uint8_t slaveAddr, uint32_t intrID)
Clears the TPS65941 interrupt function.
Board_Tps65941VoltMonitorCfg::pgoodEnable
uint8_t pgoodEnable
Definition: tps65941.h:913
Board_Tps65941WdtCfg::failThreshold
uint8_t failThreshold
Definition: tps65941.h:963
Board_Tps65941EsmCfg::maxLPTimeThreshold
uint8_t maxLPTimeThreshold
Definition: tps65941.h:984
Board_Tps65941RtcDate::date
uint8_t date
Definition: tps65941.h:942
Board_Tps65941GpioRegCfg
TPS65941 gpio details object structure.
Definition: tps65941.h:858
Board_Tps65941VoltMonitorCfg::voltOverLimit
uint8_t voltOverLimit
Definition: tps65941.h:909
Board_Tps65941EsmCfg::delay2TimeInterval
uint8_t delay2TimeInterval
Definition: tps65941.h:978
Board_tps65941ConfigIntr
Board_STATUS Board_tps65941ConfigIntr(void *handle, uint8_t slaveAddr, uint32_t intrID, uint8_t intrEnable)
TPS65941 enable/disable interrupt function.
Board_Tps65941PwrResourceRegCfg
TPS65941 power resource details object structure.
Definition: tps65941.h:873
Board_Tps65941RtcTime::meridienMode
uint8_t meridienMode
Definition: tps65941.h:933
Board_Tps65941RtcDate::week
uint8_t week
Definition: tps65941.h:948
Board_Tps65941PwrResourceRegCfg::voltageRegAddr
uint8_t voltageRegAddr
Definition: tps65941.h:879
Board_Tps65941IntrRegMap::maxReg
uint8_t maxReg
Definition: tps65941.h:894
Board_tps65941GetIntrStatus
Board_STATUS Board_tps65941GetIntrStatus(void *handle, uint8_t slaveAddr, uint32_t intrID, uint8_t *intrStatus)
Get the TPS65941 interrupt function.
Board_Tps65941PwrResourceRegCfg::cntrRegAddr
uint8_t cntrRegAddr
Definition: tps65941.h:875
Board_Tps65941PwrResourceRegCfg::cfgRegAddr
uint8_t cfgRegAddr
Definition: tps65941.h:877
Board_tps65941SetThermalThresVal
Board_STATUS Board_tps65941SetThermalThresVal(void *handle, uint8_t slaveAddr, uint32_t thermalThresholdVal)
Set the TPS65941 thermal threshold value function.
Board_Tps65941WdtCfg::win2Duration
uint8_t win2Duration
Definition: tps65941.h:961
Board_Tps65941VoltMonitorCfg::currentLimit
uint8_t currentLimit
Definition: tps65941.h:907
Board_Tps65941RtcDate::month
uint8_t month
Definition: tps65941.h:944
Board_tps65941StartEsm
Board_STATUS Board_tps65941StartEsm(void *handle, uint8_t slaveAddr, uint8_t esmCfg, uint8_t esmMode)
Start TPS65941 ESM function.
Board_tps65941GpioRead
Board_STATUS Board_tps65941GpioRead(void *handle, uint8_t slaveAddr, uint8_t pinNum, uint8_t *pinValue)
TPS65941 GPIO read function.
Board_tps65941SetVoltageMonitor
Board_STATUS Board_tps65941SetVoltageMonitor(void *handle, uint8_t slaveAddr, uint8_t powerResource, Board_Tps65941VoltMonitorCfg *voltMonCfg)
Set the voltage monitoring function.
Board_Tps65941WdtCfg::rstEnable
uint8_t rstEnable
Definition: tps65941.h:967
Board_tps65941GetThermalStatus
Board_STATUS Board_tps65941GetThermalStatus(void *handle, uint8_t slaveAddr, uint32_t *thermalStatus)
Get the TPS65941 thermal status function.
Board_Tps65941RtcTime::minutes
uint8_t minutes
Definition: tps65941.h:926
Board_Tps65941RtcTime
TPS65941 RTC time object structure.
Definition: tps65941.h:922
Board_Tps65941VoltMonitorCfg::regularEnable
uint8_t regularEnable
Definition: tps65941.h:905
Board_Tps65941VoltMonitorCfg::overVoltEnable
uint8_t overVoltEnable
Definition: tps65941.h:915
common.h
The macro definitions and function prototypes which are common across different board devices.
Board_tps65941WdtConfig
Board_STATUS Board_tps65941WdtConfig(void *handle, uint8_t slaveAddr, uint8_t wdtCfgMode, Board_Tps65941WdtCfg *wdtCfg)
TPS65941 watchdog configuration function.
Board_Tps65941WdtCfg
TPS65941 WDT configuration parameters object structure.
Definition: tps65941.h:955
Board_tps65941SetThermalMonitor
Board_STATUS Board_tps65941SetThermalMonitor(void *handle, uint8_t slaveAddr)
Set the thermal monitoring function.
Board_tps65941ConvertVolt
Board_STATUS Board_tps65941ConvertVolt(uint8_t voutCode, uint8_t powerResource, uint16_t *millivolt)
Conversion of VOUT code to millivolt.
Board_Tps65941IntrRegMap::intrRegAddr
uint8_t intrRegAddr
Definition: tps65941.h:892
Board_Tps65941IntrRegMap::maskRegAddr
uint8_t maskRegAddr
Definition: tps65941.h:890
Board_tps65941WdtDisable
Board_STATUS Board_tps65941WdtDisable(void *handle, uint8_t slaveAddr, uint8_t wdtDisable)
Enable/Disable the TPS65941 Watchdog function.
board.h
The Board Library is a thin utility layer on top of CSL and other board utilities....
Board_tps65941GpioWrite
Board_STATUS Board_tps65941GpioWrite(void *handle, uint8_t slaveAddr, uint8_t pinNum, uint8_t pinValue)
TPS65941 GPIO write function.
Board_Tps65941RtcTime::seconds
uint8_t seconds
Definition: tps65941.h:924
Board_tps65941ConvertVoutCode
Board_STATUS Board_tps65941ConvertVoutCode(uint16_t millivolt, uint8_t powerResource, uint8_t *voutCode)
Conversion of millivolt to VOUT code.
Board_Tps65941EsmCfg::minHPTimeThreshold
uint8_t minHPTimeThreshold
Definition: tps65941.h:982
Board_Tps65941EsmCfg::minLPTimeThreshold
uint8_t minLPTimeThreshold
Definition: tps65941.h:986
Board_tps65941SetTimerIntr
Board_STATUS Board_tps65941SetTimerIntr(void *handle, uint8_t slaveAddr, uint8_t timerPeriod)
Set the timer interrupt in TPS65941 RTC function.