sdl_arm_r5_mpu.h

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#ifndef SDL_ARM_R5_MPU_H
#define SDL_ARM_R5_MPU_H

#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif

typedef uint32_t SDL_ArmR5MpuRegionSize;

#define SDL_ARM_R5_MPU_REGION_SIZE_32B   (4U)

#define SDL_ARM_R5_MPU_REGION_SIZE_64B   (5U)

#define SDL_ARM_R5_MPU_REGION_SIZE_128B  (6U)

#define SDL_ARM_R5_MPU_REGION_SIZE_256B  (7U)

#define SDL_ARM_R5_MPU_REGION_SIZE_512B  (8U)

#define SDL_ARM_R5_MPU_REGION_SIZE_1KB   (9U)

#define SDL_ARM_R5_MPU_REGION_SIZE_2KB   (10U)

#define SDL_ARM_R5_MPU_REGION_SIZE_4KB   (11U)

#define SDL_ARM_R5_MPU_REGION_SIZE_8KB   (12U)

#define SDL_ARM_R5_MPU_REGION_SIZE_16KB  (13U)

#define SDL_ARM_R5_MPU_REGION_SIZE_32KB  (14U)

#define SDL_ARM_R5_MPU_REGION_SIZE_64KB  (15U)

#define SDL_ARM_R5_MPU_REGION_SIZE_128KB (16U)

#define SDL_ARM_R5_MPU_REGION_SIZE_256KB (17U)

#define SDL_ARM_R5_MPU_REGION_SIZE_512KB (18U)

#define SDL_ARM_R5_MPU_REGION_SIZE_1MB   (19U)

#define SDL_ARM_R5_MPU_REGION_SIZE_2MB   (20U)

#define SDL_ARM_R5_MPU_REGION_SIZE_4MB   (21U)

#define SDL_ARM_R5_MPU_REGION_SIZE_8MB   (22U)

#define SDL_ARM_R5_MPU_REGION_SIZE_16MB  (23U)

#define SDL_ARM_R5_MPU_REGION_SIZE_32MB  (24U)

#define SDL_ARM_R5_MPU_REGION_SIZE_64MB  (25U)

#define SDL_ARM_R5_MPU_REGION_SIZE_128MB (26U)

#define SDL_ARM_R5_MPU_REGION_SIZE_256MB (27U)

#define SDL_ARM_R5_MPU_REGION_SIZE_512MB (28U)

#define SDL_ARM_R5_MPU_REGION_SIZE_1GB   (29U)

#define SDL_ARM_R5_MPU_REGION_SIZE_2GB   (30U)

#define SDL_ARM_R5_MPU_REGION_SIZE_4GB   (31U)

/* @} */


/* @} */

#define SDL_ARM_R5F_MPU_REGIONS_MAX                 ((uint32_t) 16U)
/* @} */

#define SDL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL              ((uint32_t) 0x0U)

#define SDL_ARM_R5_MPU_SUB_REGION_0_DISABLE               ((uint32_t) 0x1U)

#define SDL_ARM_R5_MPU_SUB_REGION_1_DISABLE               ((uint32_t) 0x2U)

#define SDL_ARM_R5_MPU_SUB_REGION_2_DISABLE               ((uint32_t) 0x4U)

#define SDL_ARM_R5_MPU_SUB_REGION_3_DISABLE               ((uint32_t) 0x8U)

#define SDL_ARM_R5_MPU_SUB_REGION_4_DISABLE               ((uint32_t) 0x10U)

#define SDL_ARM_R5_MPU_SUB_REGION_5_DISABLE               ((uint32_t) 0x20U)

#define SDL_ARM_R5_MPU_SUB_REGION_6_DISABLE               ((uint32_t) 0x40U)

#define SDL_ARM_R5_MPU_SUB_REGION_8_DISABLE               ((uint32_t) 0x80U)
/* @} */

#define SDL_ARM_R5_ACC_PERM_NO_ACCESS               ((uint32_t) 0x0U)

#define SDL_ARM_R5_ACC_PERM_PRIV_RD_WR              ((uint32_t) 0x1U)

#define SDL_ARM_R5_ACC_PERM_PRIV_RD_WR_USR_RD       ((uint32_t) 0x2U)

#define SDL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR          ((uint32_t) 0x3U)

#define SDL_ARM_R5_ACC_PERM_PRIV_RD_ONLY            ((uint32_t) 0x5U)

#define SDL_ARM_R5_ACC_PERM_PRIV_USR_RD             ((uint32_t) 0x6U)
/* @} */

#define SDL_ARM_R5_CACHE_POLICY_NON_CACHEABLE               ((uint32_t) 0x0U)

#define SDL_ARM_R5_CACHE_POLICY_WB_WA                       ((uint32_t) 0x1U)

#define SDL_ARM_R5_CACHE_POLICY_WT_NO_WA                    ((uint32_t) 0x2U)

#define SDL_ARM_R5_CACHE_POLICY_WB_NO_WA                    ((uint32_t) 0x3U)
/* @} */

#define SDL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED               ((uint32_t) 0x0U)

#define SDL_ARM_R5_MEM_ATTR_SHAREABLE                      ((uint32_t) 0x1U)

#define SDL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA                ((uint32_t) 0x2U)

#define SDL_ARM_R5_MEM_ATTR_CACHED_WB_NO_WA                ((uint32_t) 0x3U)

#define SDL_ARM_R5_MEM_ATTR_STRONGLY_NON_CACHED            ((uint32_t) 0x4U)

#define SDL_ARM_R5_MEM_ATTR_CACHED_WB_WA                   ((uint32_t) 0x5U)

#define SDL_ARM_R5_MEM_ATTR_NON_SHAREABLE                  ((uint32_t) 0x6U)

#define SDL_ARM_R5_MEM_ATTR_MAX                            ((uint32_t) 0x7U)

/* @} */


/* @} */


/* MPU_REGION_BASE */

#define SDL_ARM_R5_MPU_REGION_BASE_ADDR_MASK                                       (0xFFFFFFFEU)
#define SDL_ARM_R5_MPU_REGION_BASE_ADDR_SHIFT                                      (0x00000005U)
#define SDL_ARM_R5_MPU_REGION_BASE_ADDR_RESETVAL                                   (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_BASE_ADDR_MAX                                        (0x07FFFFFFU)

/* MPU_REGION_SZEN */

#define SDL_ARM_R5_MPU_REGION_SZEN_EN_MASK                                         (0x00000001U)
#define SDL_ARM_R5_MPU_REGION_SZEN_EN_SHIFT                                        (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_SZEN_EN_RESETVAL                                     (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_SZEN_EN_MAX                                          (0x00000001U)

#define SDL_ARM_R5_MPU_REGION_SZEN_SZ_MASK                                         (0x00000037U)
#define SDL_ARM_R5_MPU_REGION_SZEN_SZ_SHIFT                                        (0x00000001U)
#define SDL_ARM_R5_MPU_REGION_SZEN_SZ_RESETVAL                                     (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_SZEN_SZ_MAX                                          (0x0000001FU)

#define SDL_ARM_R5_MPU_REGION_SZEN_SRD_MASK                                        (0x0000FF00U)
#define SDL_ARM_R5_MPU_REGION_SZEN_SRD_SHIFT                                       (0x00000008U)
#define SDL_ARM_R5_MPU_REGION_SZEN_SRD_RESETVAL                                    (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_SZEN_SRD_MAX                                         (0x000000FFU)

/* MPU_REGION_AC */

#define SDL_ARM_R5_MPU_REGION_AC_B_MASK                                            (0x00000001U)
#define SDL_ARM_R5_MPU_REGION_AC_B_SHIFT                                           (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_B_RESETVAL                                        (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_B_MAX                                             (0x00000001U)

#define SDL_ARM_R5_MPU_REGION_AC_CB_MASK                                           (0x00000003U)
#define SDL_ARM_R5_MPU_REGION_AC_CB_SHIFT                                          (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_CB_RESETVAL                                       (0x00000000U)

#define SDL_ARM_R5_MPU_REGION_AC_C_MASK                                            (0x00000002U)
#define SDL_ARM_R5_MPU_REGION_AC_C_SHIFT                                           (0x00000001U)
#define SDL_ARM_R5_MPU_REGION_AC_C_RESETVAL                                        (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_C_MAX                                             (0x00000001U)

#define SDL_ARM_R5_MPU_REGION_AC_S_MASK                                            (0x00000004U)
#define SDL_ARM_R5_MPU_REGION_AC_S_SHIFT                                           (0x00000002U)
#define SDL_ARM_R5_MPU_REGION_AC_S_RESETVAL                                        (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_S_MAX                                             (0x00000001U)

#define SDL_ARM_R5_MPU_REGION_AC_TEX_MASK                                          (0x00000038U)
#define SDL_ARM_R5_MPU_REGION_AC_TEX_SHIFT                                         (0x00000003U)
#define SDL_ARM_R5_MPU_REGION_AC_TEX_RESETVAL                                      (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_TEX_MAX                                           (0x00000007U)

#define SDL_ARM_R5_MPU_REGION_AC_AP_MASK                                           (0x00000700U)
#define SDL_ARM_R5_MPU_REGION_AC_AP_SHIFT                                          (0x00000008U)
#define SDL_ARM_R5_MPU_REGION_AC_AP_RESETVAL                                       (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_AP_MAX                                            (0x00000007U)
#define SDL_ARM_R5_MPU_REGION_AC_AP_VAL_NO_ACCESS                                  (0U)
#define SDL_ARM_R5_MPU_REGION_AC_AP_VAL_RW                                         (3U)
#define SDL_ARM_R5_MPU_REGION_AC_AP_VAL_RO                                         (6U)

#define SDL_ARM_R5_MPU_REGION_AC_XN_MASK                                           (0x00001000U)
#define SDL_ARM_R5_MPU_REGION_AC_XN_SHIFT                                          (0x0000000CU)
#define SDL_ARM_R5_MPU_REGION_AC_XN_RESETVAL                                       (0x00000000U)
#define SDL_ARM_R5_MPU_REGION_AC_XN_MAX                                            (0x00000001U)

typedef struct
{
    uint32_t regionId;
    uint32_t enable;
    uint32_t baseAddr;
    SDL_ArmR5MpuRegionSize size;
    uint32_t subRegionEnable;
    uint32_t exeNeverControl;
    uint32_t accessPermission;
    uint32_t shareable;
    uint32_t cacheable;
    uint32_t cachePolicy;
    uint32_t memAttr;
}SDL_ArmR5MpuRegionCfg;

typedef struct SDL_MPU_staticReg_read
{
    uint32_t sysControlreg;
    uint32_t mpuTypeReg;
     uint32_t regionId;
    uint32_t baseAddr;
    uint32_t size;
    uint32_t accessPermission;
}SDL_MPU_staticRegs;

/* @} */

extern void SDL_R5MPU_Enable( uint32_t enable );

extern uint32_t SDL_R5MPU_getNumRegions( void );

extern void SDL_R5MPU_Cfg( uint32_t regionNum, uint32_t baseAddrRegVal, uint32_t sizeRegVal, uint32_t accessCtrlRegVal );

extern int32_t SDL_R5MPU_VerifyCfg( uint32_t regionNum, uint32_t baseAddrRegVal, uint32_t sizeRegVal, uint32_t accessCtrlRegVal );

extern void SDL_R5FMPU_enableRegion( uint32_t regionNum, uint32_t enable );

extern int32_t SDL_R5MPU_VerifyEnableRegion( uint32_t regionNum, uint32_t enable );

extern void SDL_R5MPU_readStaticRegisters(SDL_MPU_staticRegs *pStaticRegs,uint32_t regionNum);  
    
/* @} */

#ifdef __cplusplus
}
#endif  /* extern "C" */

#endif  /* end of SDL_ARM_R5_MPU_H definition */