SDL API Guide for J721E
sdlr_ecc.h
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2  * Copyright (C) 2021 Texas Instruments Incorporated.
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30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * Name : sdlr_ecc.h
33 */
34 #ifndef SDLR_ECC_AGGR_H_
35 #define SDLR_ECC_AGGR_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 #include <sdlr.h>
42 #include <stdint.h>
43 
44 /**************************************************************************
45 * Hardware Region :
46 **************************************************************************/
47 
48 
49 /**************************************************************************
50 * Register Overlay Structure
51 **************************************************************************/
52 
53 typedef struct {
54  volatile uint32_t REV; /* Aggregator Revision Register */
55  volatile uint8_t Resv_8[4];
56  volatile uint32_t VECTOR; /* ECC Vector Register */
57  volatile uint32_t STAT; /* Misc Status */
58  volatile uint32_t RESERVED_SVBUS[8]; /* Reserved Area for Serial VBUS Registers */
59  volatile uint8_t Resv_60[12];
60  volatile uint32_t SEC_EOI_REG; /* EOI Register */
61  volatile uint32_t SEC_STATUS_REG0; /* Interrupt Status Register 0 */
62  volatile uint8_t Resv_128[60];
63  volatile uint32_t SEC_ENABLE_SET_REG0; /* Interrupt Enable Set Register 0 */
64  volatile uint8_t Resv_192[60];
65  volatile uint32_t SEC_ENABLE_CLR_REG0; /* Interrupt Enable Clear Register 0 */
66  volatile uint8_t Resv_316[120];
67  volatile uint32_t DED_EOI_REG; /* EOI Register */
68  volatile uint32_t DED_STATUS_REG0; /* Interrupt Status Register 0 */
69  volatile uint8_t Resv_384[60];
70  volatile uint32_t DED_ENABLE_SET_REG0; /* Interrupt Enable Set Register 0 */
71  volatile uint8_t Resv_448[60];
72  volatile uint32_t DED_ENABLE_CLR_REG0; /* Interrupt Enable Clear Register 0 */
73  volatile uint8_t Resv_512[60];
74  volatile uint32_t AGGR_ENABLE_SET; /* AGGR interrupt enable set Register */
75  volatile uint32_t AGGR_ENABLE_CLR; /* AGGR interrupt enable clear Register */
76  volatile uint32_t AGGR_STATUS_SET; /* AGGR interrupt status set Register */
77  volatile uint32_t AGGR_STATUS_CLR; /* AGGR interrupt status clear Register */
78 } SDL_ecc_aggrRegs;
79 
80 
81 /**************************************************************************
82 * Register Macros
83 **************************************************************************/
84 
85 #define SDL_ECC_AGGR_REV (0x00000000U)
86 #define SDL_ECC_AGGR_VECTOR (0x00000008U)
87 #define SDL_ECC_AGGR_STAT (0x0000000CU)
88 #define SDL_ECC_AGGR_RESERVED_SVBUS(RESERVED_SVBUS) (0x00000010U+((RESERVED_SVBUS)*0x4U))
89 #define SDL_ECC_AGGR_SEC_EOI_REG (0x0000003CU)
90 #define SDL_ECC_AGGR_SEC_STATUS_REG0 (0x00000040U)
91 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0 (0x00000080U)
92 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0 (0x000000C0U)
93 #define SDL_ECC_AGGR_DED_EOI_REG (0x0000013CU)
94 #define SDL_ECC_AGGR_DED_STATUS_REG0 (0x00000140U)
95 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0 (0x00000180U)
96 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0 (0x000001C0U)
97 #define SDL_ECC_AGGR_AGGR_ENABLE_SET (0x00000200U)
98 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR (0x00000204U)
99 #define SDL_ECC_AGGR_AGGR_STATUS_SET (0x00000208U)
100 #define SDL_ECC_AGGR_AGGR_STATUS_CLR (0x0000020CU)
101 
102 /**************************************************************************
103 * Field Definition Macros
104 **************************************************************************/
105 
106 
107 /* REV */
108 
109 #define SDL_ECC_AGGR_REV_SCHEME_MASK (0xC0000000U)
110 #define SDL_ECC_AGGR_REV_SCHEME_SHIFT (0x0000001EU)
111 #define SDL_ECC_AGGR_REV_SCHEME_MAX (0x00000003U)
112 
113 #define SDL_ECC_AGGR_REV_BU_MASK (0x30000000U)
114 #define SDL_ECC_AGGR_REV_BU_SHIFT (0x0000001CU)
115 #define SDL_ECC_AGGR_REV_BU_MAX (0x00000003U)
116 
117 #define SDL_ECC_AGGR_REV_MODULE_ID_MASK (0x0FFF0000U)
118 #define SDL_ECC_AGGR_REV_MODULE_ID_SHIFT (0x00000010U)
119 #define SDL_ECC_AGGR_REV_MODULE_ID_MAX (0x00000FFFU)
120 
121 #define SDL_ECC_AGGR_REV_REVRTL_MASK (0x0000F800U)
122 #define SDL_ECC_AGGR_REV_REVRTL_SHIFT (0x0000000BU)
123 #define SDL_ECC_AGGR_REV_REVRTL_MAX (0x0000001FU)
124 
125 #define SDL_ECC_AGGR_REV_REVMAJ_MASK (0x00000700U)
126 #define SDL_ECC_AGGR_REV_REVMAJ_SHIFT (0x00000008U)
127 #define SDL_ECC_AGGR_REV_REVMAJ_MAX (0x00000007U)
128 
129 #define SDL_ECC_AGGR_REV_CUSTOM_MASK (0x000000C0U)
130 #define SDL_ECC_AGGR_REV_CUSTOM_SHIFT (0x00000006U)
131 #define SDL_ECC_AGGR_REV_CUSTOM_MAX (0x00000003U)
132 
133 #define SDL_ECC_AGGR_REV_REVMIN_MASK (0x0000003FU)
134 #define SDL_ECC_AGGR_REV_REVMIN_SHIFT (0x00000000U)
135 #define SDL_ECC_AGGR_REV_REVMIN_MAX (0x0000003FU)
136 
137 /* VECTOR */
138 
139 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MASK (0x000007FFU)
140 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_SHIFT (0x00000000U)
141 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MAX (0x000007FFU)
142 
143 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MASK (0x00008000U)
144 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_SHIFT (0x0000000FU)
145 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MAX (0x00000001U)
146 
147 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MASK (0x00FF0000U)
148 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_SHIFT (0x00000010U)
149 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MAX (0x000000FFU)
150 
151 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MASK (0x01000000U)
152 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_SHIFT (0x00000018U)
153 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MAX (0x00000001U)
154 
155 /* STAT */
156 
157 #define SDL_ECC_AGGR_STAT_NUM_RAMS_MASK (0x000007FFU)
158 #define SDL_ECC_AGGR_STAT_NUM_RAMS_SHIFT (0x00000000U)
159 #define SDL_ECC_AGGR_STAT_NUM_RAMS_MAX (0x000007FFU)
160 
161 /* RESERVED_SVBUS */
162 
163 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MASK (0xFFFFFFFFU)
164 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_SHIFT (0x00000000U)
165 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MAX (0xFFFFFFFFU)
166 
167 /* SEC_EOI_REG */
168 
169 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MASK (0x00000001U)
170 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_SHIFT (0x00000000U)
171 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MAX (0x00000001U)
172 
173 /* SEC_STATUS_REG0 */
174 
175 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)
176 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)
177 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)
178 
179 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)
180 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)
181 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)
182 
183 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)
184 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)
185 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)
186 
187 /* SEC_ENABLE_SET_REG0 */
188 
189 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)
190 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)
191 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)
192 
193 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)
194 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)
195 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)
196 
197 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)
198 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)
199 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)
200 
201 /* SEC_ENABLE_CLR_REG0 */
202 
203 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)
204 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)
205 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)
206 
207 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)
208 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)
209 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)
210 
211 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)
212 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)
213 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)
214 
215 /* DED_EOI_REG */
216 
217 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MASK (0x00000001U)
218 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_SHIFT (0x00000000U)
219 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MAX (0x00000001U)
220 
221 /* DED_STATUS_REG0 */
222 
223 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)
224 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)
225 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)
226 
227 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)
228 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)
229 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)
230 
231 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)
232 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)
233 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)
234 
235 /* DED_ENABLE_SET_REG0 */
236 
237 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)
238 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)
239 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)
240 
241 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)
242 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)
243 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)
244 
245 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)
246 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)
247 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)
248 
249 /* DED_ENABLE_CLR_REG0 */
250 
251 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)
252 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)
253 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)
254 
255 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)
256 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)
257 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)
258 
259 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)
260 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)
261 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)
262 
263 /* AGGR_ENABLE_SET */
264 
265 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MASK (0x00000001U)
266 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_SHIFT (0x00000000U)
267 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MAX (0x00000001U)
268 
269 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MASK (0x00000002U)
270 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_SHIFT (0x00000001U)
271 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MAX (0x00000001U)
272 
273 /* AGGR_ENABLE_CLR */
274 
275 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MASK (0x00000001U)
276 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_SHIFT (0x00000000U)
277 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MAX (0x00000001U)
278 
279 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MASK (0x00000002U)
280 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_SHIFT (0x00000001U)
281 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MAX (0x00000001U)
282 
283 /* AGGR_STATUS_SET */
284 
285 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MASK (0x00000003U)
286 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_SHIFT (0x00000000U)
287 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MAX (0x00000003U)
288 
289 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MASK (0x0000000CU)
290 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_SHIFT (0x00000002U)
291 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MAX (0x00000003U)
292 
293 /* AGGR_STATUS_CLR */
294 
295 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MASK (0x00000003U)
296 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_SHIFT (0x00000000U)
297 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MAX (0x00000003U)
298 
299 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MASK (0x0000000CU)
300 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_SHIFT (0x00000002U)
301 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MAX (0x00000003U)
302 
303 #ifdef __cplusplus
304 }
305 #endif
306 #endif
SDL_ecc_aggrRegs::AGGR_STATUS_CLR
volatile uint32_t AGGR_STATUS_CLR
Definition: sdlr_ecc.h:77
SDL_ecc_aggrRegs::DED_EOI_REG
volatile uint32_t DED_EOI_REG
Definition: sdlr_ecc.h:67
SDL_ecc_aggrRegs::DED_ENABLE_SET_REG0
volatile uint32_t DED_ENABLE_SET_REG0
Definition: sdlr_ecc.h:70
SDL_ecc_aggrRegs::SEC_EOI_REG
volatile uint32_t SEC_EOI_REG
Definition: sdlr_ecc.h:60
SDL_ecc_aggrRegs::DED_STATUS_REG0
volatile uint32_t DED_STATUS_REG0
Definition: sdlr_ecc.h:68
SDL_ecc_aggrRegs::VECTOR
volatile uint32_t VECTOR
Definition: sdlr_ecc.h:56
SDL_ecc_aggrRegs::STAT
volatile uint32_t STAT
Definition: sdlr_ecc.h:57
SDL_ecc_aggrRegs::AGGR_ENABLE_CLR
volatile uint32_t AGGR_ENABLE_CLR
Definition: sdlr_ecc.h:75
SDL_ecc_aggrRegs::SEC_ENABLE_CLR_REG0
volatile uint32_t SEC_ENABLE_CLR_REG0
Definition: sdlr_ecc.h:65
SDL_ecc_aggrRegs
Definition: sdlr_ecc.h:53
SDL_ecc_aggrRegs::SEC_STATUS_REG0
volatile uint32_t SEC_STATUS_REG0
Definition: sdlr_ecc.h:61
SDL_ecc_aggrRegs::AGGR_ENABLE_SET
volatile uint32_t AGGR_ENABLE_SET
Definition: sdlr_ecc.h:74
SDL_ecc_aggrRegs::DED_ENABLE_CLR_REG0
volatile uint32_t DED_ENABLE_CLR_REG0
Definition: sdlr_ecc.h:72
SDL_ecc_aggrRegs::AGGR_STATUS_SET
volatile uint32_t AGGR_STATUS_SET
Definition: sdlr_ecc.h:76
SDL_ecc_aggrRegs::SEC_ENABLE_SET_REG0
volatile uint32_t SEC_ENABLE_SET_REG0
Definition: sdlr_ecc.h:63
SDL_ecc_aggrRegs::REV
volatile uint32_t REV
Definition: sdlr_ecc.h:54