SDL API Guide for J721E
sdlr_esm.h
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30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  * Name : sdlr_esm.h
33 */
34 #ifndef SDLR_ESM_H_
35 #define SDLR_ESM_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 #include <sdlr.h>
42 #include <stdint.h>
43 
44 /**************************************************************************
45 * Module Base Offset Values
46 **************************************************************************/
47 
48 #define SDL_ESM_REGS_BASE (0x00000000U)
49 
50 
51 /**************************************************************************
52 * Hardware Region : ESM Registers
53 **************************************************************************/
54 
55 
56 /**************************************************************************
57 * Register Overlay Structure
58 **************************************************************************/
59 
60 typedef struct {
61  volatile uint32_t RAW; /* Config Error Raw Status/Set Register */
62  volatile uint32_t STS; /* Level Error Interrupt Enable Status/Clear Register */
63  volatile uint32_t INTR_EN_SET; /* Level Error Interrutp Enable Set Register */
64  volatile uint32_t INTR_EN_CLR; /* Level Error Interrupt Enabled Clear Register */
65  volatile uint32_t INT_PRIO; /* Level Error Interrupt Enabled Clear Register */
66  volatile uint32_t PIN_EN_SET; /* Level Error Interrupt Enabled Clear Register */
67  volatile uint32_t PIN_EN_CLR; /* Level Error Interrupt Enabled Clear Register */
68  volatile uint8_t Resv_32[4];
69 } SDL_esmRegs_ERR_GRP;
70 
71 
72 typedef struct {
73  volatile uint32_t PID; /* Revision Register */
74  volatile uint32_t INFO; /* Info Register */
75  volatile uint32_t EN; /* Global Enable Register */
76  volatile uint32_t SFT_RST; /* Global Soft Reset Register */
77  volatile uint32_t ERR_RAW; /* Config Error Raw Status/Set Register */
78  volatile uint32_t ERR_STS; /* Config Error Interrupt Enable Status/Clear Register */
79  volatile uint32_t ERR_EN_SET; /* Config Error Interrutp Enable Set Register */
80  volatile uint32_t ERR_EN_CLR; /* Config Error Interrupt Enabled Clear Register */
81  volatile uint32_t LOW_PRI; /* Low Priority Prioritized Register */
82  volatile uint32_t HI_PRI; /* High Priority Prioritized Register */
83  volatile uint32_t LOW; /* Low Priority Interrupt Status Register */
84  volatile uint32_t HI; /* High Priority Interrupt Status Register */
85  volatile uint32_t EOI; /* EOI Interrupt Register */
86  volatile uint8_t Resv_64[12];
87  volatile uint32_t PIN_CTRL; /* Error Pin Control Register */
88  volatile uint32_t PIN_STS; /* Error Pin Status Register */
89  volatile uint32_t PIN_CNTR; /* Error Counter Value Register */
90  volatile uint32_t PIN_CNTR_PRE; /* Error Counter Value Pre-Load Register */
91  volatile uint8_t Resv_1024[944];
92  SDL_esmRegs_ERR_GRP ERR_GRP[32];
93 } SDL_esmRegs;
94 
95 
96 /**************************************************************************
97 * Register Macros
98 **************************************************************************/
99 
100 #define SDL_ESM_PID (0x00000000U)
101 #define SDL_ESM_INFO (0x00000004U)
102 #define SDL_ESM_EN (0x00000008U)
103 #define SDL_ESM_SFT_RST (0x0000000CU)
104 #define SDL_ESM_ERR_RAW (0x00000010U)
105 #define SDL_ESM_ERR_STS (0x00000014U)
106 #define SDL_ESM_ERR_EN_SET (0x00000018U)
107 #define SDL_ESM_ERR_EN_CLR (0x0000001CU)
108 #define SDL_ESM_LOW_PRI (0x00000020U)
109 #define SDL_ESM_HI_PRI (0x00000024U)
110 #define SDL_ESM_LOW (0x00000028U)
111 #define SDL_ESM_HI (0x0000002CU)
112 #define SDL_ESM_EOI (0x00000030U)
113 #define SDL_ESM_PIN_CTRL (0x00000040U)
114 #define SDL_ESM_PIN_STS (0x00000044U)
115 #define SDL_ESM_PIN_CNTR (0x00000048U)
116 #define SDL_ESM_PIN_CNTR_PRE (0x0000004CU)
117 #define SDL_ESM_ERR_GRP_RAW(ERR_GRP) (0x00000400U+((ERR_GRP)*0x20U))
118 #define SDL_ESM_ERR_GRP_STS(ERR_GRP) (0x00000404U+((ERR_GRP)*0x20U))
119 #define SDL_ESM_ERR_GRP_INTR_EN_SET(ERR_GRP) (0x00000408U+((ERR_GRP)*0x20U))
120 #define SDL_ESM_ERR_GRP_INTR_EN_CLR(ERR_GRP) (0x0000040CU+((ERR_GRP)*0x20U))
121 #define SDL_ESM_ERR_GRP_INT_PRIO(ERR_GRP) (0x00000410U+((ERR_GRP)*0x20U))
122 #define SDL_ESM_ERR_GRP_PIN_EN_SET(ERR_GRP) (0x00000414U+((ERR_GRP)*0x20U))
123 #define SDL_ESM_ERR_GRP_PIN_EN_CLR(ERR_GRP) (0x00000418U+((ERR_GRP)*0x20U))
124 
125 /**************************************************************************
126 * Field Definition Macros
127 **************************************************************************/
128 
129 
130 /* RAW */
131 
132 #define SDL_ESM_ERR_GRP_RAW_STS_MASK (0xFFFFFFFFU)
133 #define SDL_ESM_ERR_GRP_RAW_STS_SHIFT (0x00000000U)
134 #define SDL_ESM_ERR_GRP_RAW_STS_MAX (0xFFFFFFFFU)
135 
136 /* STS */
137 
138 #define SDL_ESM_ERR_GRP_STS_MSK_MASK (0xFFFFFFFFU)
139 #define SDL_ESM_ERR_GRP_STS_MSK_SHIFT (0x00000000U)
140 #define SDL_ESM_ERR_GRP_STS_MSK_MAX (0xFFFFFFFFU)
141 
142 /* INTR_EN_SET */
143 
144 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MASK (0xFFFFFFFFU)
145 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U)
146 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MAX (0xFFFFFFFFU)
147 
148 /* INTR_EN_CLR */
149 
150 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
151 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U)
152 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
153 
154 /* INT_PRIO */
155 
156 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MASK (0xFFFFFFFFU)
157 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_SHIFT (0x00000000U)
158 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MAX (0xFFFFFFFFU)
159 
160 /* PIN_EN_SET */
161 
162 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MASK (0xFFFFFFFFU)
163 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_SHIFT (0x00000000U)
164 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MAX (0xFFFFFFFFU)
165 
166 /* PIN_EN_CLR */
167 
168 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MASK (0xFFFFFFFFU)
169 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_SHIFT (0x00000000U)
170 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MAX (0xFFFFFFFFU)
171 
172 /* PID */
173 
174 #define SDL_ESM_PID_MINOR_MASK (0x0000003FU)
175 #define SDL_ESM_PID_MINOR_SHIFT (0x00000000U)
176 #define SDL_ESM_PID_MINOR_MAX (0x0000003FU)
177 
178 #define SDL_ESM_PID_CUSTOM_MASK (0x000000C0U)
179 #define SDL_ESM_PID_CUSTOM_SHIFT (0x00000006U)
180 #define SDL_ESM_PID_CUSTOM_MAX (0x00000003U)
181 
182 #define SDL_ESM_PID_MAJOR_MASK (0x00000700U)
183 #define SDL_ESM_PID_MAJOR_SHIFT (0x00000008U)
184 #define SDL_ESM_PID_MAJOR_MAX (0x00000007U)
185 
186 #define SDL_ESM_PID_RTL_MASK (0x0000F800U)
187 #define SDL_ESM_PID_RTL_SHIFT (0x0000000BU)
188 #define SDL_ESM_PID_RTL_MAX (0x0000001FU)
189 
190 #define SDL_ESM_PID_FUNC_MASK (0x0FFF0000U)
191 #define SDL_ESM_PID_FUNC_SHIFT (0x00000010U)
192 #define SDL_ESM_PID_FUNC_MAX (0x00000FFFU)
193 
194 #define SDL_ESM_PID_BU_MASK (0x30000000U)
195 #define SDL_ESM_PID_BU_SHIFT (0x0000001CU)
196 #define SDL_ESM_PID_BU_MAX (0x00000003U)
197 
198 #define SDL_ESM_PID_SCHEME_MASK (0xC0000000U)
199 #define SDL_ESM_PID_SCHEME_SHIFT (0x0000001EU)
200 #define SDL_ESM_PID_SCHEME_MAX (0x00000003U)
201 
202 /* INFO */
203 
204 #define SDL_ESM_INFO_GROUPS_MASK (0x000000FFU)
205 #define SDL_ESM_INFO_GROUPS_SHIFT (0x00000000U)
206 #define SDL_ESM_INFO_GROUPS_MAX (0x000000FFU)
207 
208 #define SDL_ESM_INFO_PULSE_GROUPS_MASK (0x0000FF00U)
209 #define SDL_ESM_INFO_PULSE_GROUPS_SHIFT (0x00000008U)
210 #define SDL_ESM_INFO_PULSE_GROUPS_MAX (0x000000FFU)
211 
212 #define SDL_ESM_INFO_LAST_RESET_MASK (0x80000000U)
213 #define SDL_ESM_INFO_LAST_RESET_SHIFT (0x0000001FU)
214 #define SDL_ESM_INFO_LAST_RESET_MAX (0x00000001U)
215 
216 /* EN */
217 
218 #define SDL_ESM_EN_KEY_MASK (0x0000000FU)
219 #define SDL_ESM_EN_KEY_SHIFT (0x00000000U)
220 #define SDL_ESM_EN_KEY_MAX (0x0000000FU)
221 
222 /* SFT_RST */
223 
224 #define SDL_ESM_SFT_RST_KEY_MASK (0x0000000FU)
225 #define SDL_ESM_SFT_RST_KEY_SHIFT (0x00000000U)
226 #define SDL_ESM_SFT_RST_KEY_MAX (0x0000000FU)
227 
228 /* ERR_RAW */
229 
230 #define SDL_ESM_ERR_RAW_STS_MASK (0xFFFFFFFFU)
231 #define SDL_ESM_ERR_RAW_STS_SHIFT (0x00000000U)
232 #define SDL_ESM_ERR_RAW_STS_MAX (0xFFFFFFFFU)
233 
234 /* ERR_STS */
235 
236 #define SDL_ESM_ERR_STS_MSK_MASK (0xFFFFFFFFU)
237 #define SDL_ESM_ERR_STS_MSK_SHIFT (0x00000000U)
238 #define SDL_ESM_ERR_STS_MSK_MAX (0xFFFFFFFFU)
239 
240 /* ERR_EN_SET */
241 
242 #define SDL_ESM_ERR_EN_SET_MSK_MASK (0xFFFFFFFFU)
243 #define SDL_ESM_ERR_EN_SET_MSK_SHIFT (0x00000000U)
244 #define SDL_ESM_ERR_EN_SET_MSK_MAX (0xFFFFFFFFU)
245 
246 /* ERR_EN_CLR */
247 
248 #define SDL_ESM_ERR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
249 #define SDL_ESM_ERR_EN_CLR_MSK_SHIFT (0x00000000U)
250 #define SDL_ESM_ERR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
251 
252 /* LOW_PRI */
253 
254 #define SDL_ESM_LOW_PRI_PLS_MASK (0xFFFF0000U)
255 #define SDL_ESM_LOW_PRI_PLS_SHIFT (0x00000010U)
256 #define SDL_ESM_LOW_PRI_PLS_MAX (0x0000FFFFU)
257 
258 #define SDL_ESM_LOW_PRI_LVL_MASK (0x0000FFFFU)
259 #define SDL_ESM_LOW_PRI_LVL_SHIFT (0x00000000U)
260 #define SDL_ESM_LOW_PRI_LVL_MAX (0x0000FFFFU)
261 
262 /* HI_PRI */
263 
264 #define SDL_ESM_HI_PRI_PLS_MASK (0xFFFF0000U)
265 #define SDL_ESM_HI_PRI_PLS_SHIFT (0x00000010U)
266 #define SDL_ESM_HI_PRI_PLS_MAX (0x0000FFFFU)
267 
268 #define SDL_ESM_HI_PRI_LVL_MASK (0x0000FFFFU)
269 #define SDL_ESM_HI_PRI_LVL_SHIFT (0x00000000U)
270 #define SDL_ESM_HI_PRI_LVL_MAX (0x0000FFFFU)
271 
272 /* LOW */
273 
274 #define SDL_ESM_LOW_STS_MASK (0xFFFFFFFFU)
275 #define SDL_ESM_LOW_STS_SHIFT (0x00000000U)
276 #define SDL_ESM_LOW_STS_MAX (0xFFFFFFFFU)
277 
278 /* HI */
279 
280 #define SDL_ESM_HI_STS_MASK (0xFFFFFFFFU)
281 #define SDL_ESM_HI_STS_SHIFT (0x00000000U)
282 #define SDL_ESM_HI_STS_MAX (0xFFFFFFFFU)
283 
284 /* EOI */
285 
286 #define SDL_ESM_EOI_KEY_MASK (0x000007FFU)
287 #define SDL_ESM_EOI_KEY_SHIFT (0x00000000U)
288 #define SDL_ESM_EOI_KEY_MAX (0x000007FFU)
289 
290 /* PIN_CTRL */
291 
292 #define SDL_ESM_PIN_CTRL_KEY_MASK (0x0000000FU)
293 #define SDL_ESM_PIN_CTRL_KEY_SHIFT (0x00000000U)
294 #define SDL_ESM_PIN_CTRL_KEY_MAX (0x0000000FU)
295 
296 /* PIN_STS */
297 
298 #define SDL_ESM_PIN_STS_VAL_MASK (0x00000001U)
299 #define SDL_ESM_PIN_STS_VAL_SHIFT (0x00000000U)
300 #define SDL_ESM_PIN_STS_VAL_MAX (0x00000001U)
301 
302 /* PIN_CNTR */
303 
304 #define SDL_ESM_PIN_CNTR_COUNT_MASK (0x00FFFFFFU)
305 #define SDL_ESM_PIN_CNTR_COUNT_SHIFT (0x00000000U)
306 #define SDL_ESM_PIN_CNTR_COUNT_MAX (0x00FFFFFFU)
307 
308 /* PIN_CNTR_PRE */
309 
310 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MASK (0x00FFFFFFU)
311 #define SDL_ESM_PIN_CNTR_PRE_COUNT_SHIFT (0x00000000U)
312 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MAX (0x00FFFFFFU)
313 
314 #ifdef __cplusplus
315 }
316 #endif
317 #endif /* SDLR_ESM_ */
SDL_esmRegs_ERR_GRP::RAW
volatile uint32_t RAW
Definition: sdlr_esm.h:61
SDL_esmRegs::ERR_STS
volatile uint32_t ERR_STS
Definition: sdlr_esm.h:78
SDL_esmRegs::EOI
volatile uint32_t EOI
Definition: sdlr_esm.h:85
SDL_esmRegs::SFT_RST
volatile uint32_t SFT_RST
Definition: sdlr_esm.h:76
SDL_esmRegs::EN
volatile uint32_t EN
Definition: sdlr_esm.h:75
SDL_esmRegs
Definition: sdlr_esm.h:72
SDL_esmRegs::INFO
volatile uint32_t INFO
Definition: sdlr_esm.h:74
SDL_esmRegs::ERR_EN_CLR
volatile uint32_t ERR_EN_CLR
Definition: sdlr_esm.h:80
SDL_esmRegs::PIN_CNTR_PRE
volatile uint32_t PIN_CNTR_PRE
Definition: sdlr_esm.h:90
SDL_esmRegs::LOW_PRI
volatile uint32_t LOW_PRI
Definition: sdlr_esm.h:81
SDL_esmRegs::LOW
volatile uint32_t LOW
Definition: sdlr_esm.h:83
SDL_esmRegs_ERR_GRP::PIN_EN_CLR
volatile uint32_t PIN_EN_CLR
Definition: sdlr_esm.h:67
SDL_esmRegs::HI
volatile uint32_t HI
Definition: sdlr_esm.h:84
SDL_esmRegs::PIN_CTRL
volatile uint32_t PIN_CTRL
Definition: sdlr_esm.h:87
SDL_esmRegs::ERR_EN_SET
volatile uint32_t ERR_EN_SET
Definition: sdlr_esm.h:79
SDL_esmRegs_ERR_GRP
Definition: sdlr_esm.h:60
SDL_esmRegs_ERR_GRP::INTR_EN_SET
volatile uint32_t INTR_EN_SET
Definition: sdlr_esm.h:63
SDL_esmRegs::ERR_RAW
volatile uint32_t ERR_RAW
Definition: sdlr_esm.h:77
SDL_esmRegs_ERR_GRP::INTR_EN_CLR
volatile uint32_t INTR_EN_CLR
Definition: sdlr_esm.h:64
SDL_esmRegs::PIN_STS
volatile uint32_t PIN_STS
Definition: sdlr_esm.h:88
SDL_esmRegs_ERR_GRP::STS
volatile uint32_t STS
Definition: sdlr_esm.h:62
SDL_esmRegs::HI_PRI
volatile uint32_t HI_PRI
Definition: sdlr_esm.h:82
SDL_esmRegs::PID
volatile uint32_t PID
Definition: sdlr_esm.h:73
SDL_esmRegs_ERR_GRP::INT_PRIO
volatile uint32_t INT_PRIO
Definition: sdlr_esm.h:65
SDL_esmRegs::PIN_CNTR
volatile uint32_t PIN_CNTR
Definition: sdlr_esm.h:89
SDL_esmRegs_ERR_GRP::PIN_EN_SET
volatile uint32_t PIN_EN_SET
Definition: sdlr_esm.h:66