TIOVX User Guide
TIOVX Supported Kernels

Table of Contents

Legend

Meaning of terms in the following tables,

  • DMA: Kernel implemented and memory access done using DMA (NOTE: Not enabled in this release)
  • Cache: Kernel implemented and memory access done using CPU Cache
  • [empty]: Kernel is not supported on target

OpenVX Standard Kernels

This table lists the mapping of standard OpenVX kernels to compute targets on the Jacinto7 platform. When mapped to C66x DSP, it indicates if it is implemented using BAM DMA acceleration, or cache only.

All of the below kernels default to running on the C66x DSP 1. If a different target is needed, it can be selected from the available targets indicated below by using the vxSetNodeTarget() API.

Kernel C66x 1 C66x 2 HWA
Absolute Difference Cache Cache Yes
Accumulate Cache Cache Yes
Accumulate Squared Cache Cache Yes
Accumulate Weighted Cache Cache Yes
Arithmetic Addition Cache Cache Yes
Arithmetic Subtraction Cache Cache Yes
Bitwise AND Cache Cache Yes
Bitwise EXCLUSIVE OR Cache Cache Yes
Bitwise INCLUSIVE OR Cache Cache Yes
Bitwise NOT Cache Cache Yes
Box Filter Cache Cache Yes
Canny Edge Detector Cache Cache Yes
Channel Combine Cache Cache Yes
Channel Extract Cache Cache Yes
Color Convert Cache Cache Yes
Convert Bit depth Cache Cache Yes
Custom Convolution Cache Cache Yes
Dilate Image Cache Cache Yes
Equalize Histogram Cache Cache Yes
Erode Image Cache Cache Yes
Fast Corners Cache Cache Yes
Gaussian Filter Cache Cache Yes
Non Linear Filter Cache Cache Yes
Harris Corners Cache Cache Yes
Histogram Cache Cache Yes
Gaussian Image Pyramid Cache Cache VPAC_MSC* Yes
Laplacian Image Pyramid Cache Cache Yes
Reconstruction from a Laplacian Image Pyramid Cache Cache Yes
Integral Image Cache Cache Yes
Magnitude Cache Cache Yes
Mean and Standard Deviation Cache Cache Yes
Median Filter Cache Cache Yes
Min, Max Location Cache Cache Yes
Optical Flow Pyramid (LK) Cache Cache Yes
Phase Cache Cache Yes
Pixel-wise Multiplication Cache Cache Yes
Remap Cache Cache Yes
Scale Image Cache Cache VPAC_MSC* Yes
Sobel 3x3 Cache Cache Yes
TableLookup Cache Cache Yes
Thresholding Cache Cache Yes
Warp Affine Cache Cache Yes
Warp Perspective Cache Cache Yes
  • Subset of configuration options and or accuracy tradeoff to speed is to be considered for this HWA implementation.

TI Extension Kernels

Note: the below node implementation locations have changed from the 8.6 to 9.0 releases. The new locations can be referenced in Directory Structure document.

Kernel Target PC Emulation Support
tivxCaptureNode CSIRX No
tivxDisplayNode DSS No
tivxTIDLNode C7x + MMA Yes
tivxVpacVissNode VPAC_VISS Yes
tivxVpacLdcNode VPAC_LDC Yes
tivxVpacNfGenericNode VPAC_NF Yes
tivxVpacNfBilateralNode VPAC_NF Yes
tivxVpacMscScaleNode VPAC_MSC Yes
tivxVpacMscPyramidNode VPAC_MSC Yes
tivxDmpacSdeNode DMPAC_SDE Yes
tivxDmpacDofNode DMPAC_DOF Yes
tivxCsitxNode CSITX No
tivxDisplayM2MNode DSS No