88 #ifndef CDD_IPC_CFG_H_ 89 #define CDD_IPC_CFG_H_ 104 #include <CddIpc/ipc_baremetal_hw/include/ipc_config.h> 124 #define CDD_IPC_PRE_COMPILE_VARIANT (STD_ON) 132 #define CDD_IPC_DEV_ERROR_DETECT (STD_ON) 140 #define CDD_IPC_ISR_TYPE (CDD_IPC_ISR_CAT2) 153 #define CDD_IPC_VERSION_INFO_API (STD_ON) 161 #define CDD_IPC_DEINIT_API (STD_ON) 169 #define CDD_IPC_ANNOUNCE_API (STD_ON) 177 #define CDD_IPC_REGISTER_READBACK_API (STD_ON) 185 #define CDD_IPC_SAFETY_DIAGNOSTIC_API (STD_ON) 194 #define CDD_IPC_IS_INIT_DONE_API (STD_ON) 204 #define CDD_IPC_GET_MAX_MSG_SIZE_API (STD_ON) 220 #define CDD_IPC_OS_COUNTER_ID ((CounterType)OsCounter_0) 234 #define DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT (0xFFFFU) 235 #define CDD_IPC_DEM_NO_EVENT DemConf_DemEventParameter_CDD_IPC_DEM_NO_EVENT 237 #ifndef CDD_IPC_E_HARDWARE_ERROR 239 #define CDD_IPC_E_HARDWARE_ERROR (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR) 253 #define CDD_IPC_CORE_MCU1_0 (1U) 255 #define CDD_IPC_CORE_MCU1_1 (2U) 257 #define CDD_IPC_CORE_MCU2_0 (3U) 259 #define CDD_IPC_CORE_MCU2_1 (4U) 261 #define CDD_IPC_CORE_MCU3_0 (5U) 263 #define CDD_IPC_CORE_MCU3_1 (6U) 265 #define CDD_IPC_CORE_C66X_1 (7U) 267 #define CDD_IPC_CORE_C66X_2 (8U) 269 #define CDD_IPC_CORE_C7X_1 (9U) 271 #define CDD_IPC_CORE_MAX_PROCS (11U) 275 #define CDD_IPC_OWN_CORE_ID (CDD_IPC_CORE_MCU1_0) 277 #define CDD_IPC_REMOTE_CORE_MCU2_0_USED 279 #define CDD_IPC_REMOTE_CORE_MCU2_1_USED 295 #define CDD_IPC_VERTIO_OBJECT_SIZE (0x1000U) 308 #define CddIpcConf_IpcComChanId_Cdd_IpcMcu20 (0U) 310 #define CddIpcConf_IpcComChanId_Cdd_IpcMcu21 (1U) 319 #define CDD_IPC_RPMSG_OBJ_SIZE (256U) 321 #define CDD_IPC_CH_0_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE) 323 #define CDD_IPC_CH_1_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE) 325 #define CDD_IPC_MAX_CHANNEL_CFG (2U) 332 #define IPC_VRING_BUFFER_SIZE (0x1C00000U) 335 #define IPC_MPU1_0 (0U) 336 #define IPC_MCU1_0 (1U) 337 #define IPC_MCU1_1 (2U) 338 #define IPC_MCU2_0 (3U) 339 #define IPC_MCU2_1 (4U) 340 #define IPC_MCU3_0 (5U) 341 #define IPC_MCU3_1 (6U) 342 #define IPC_C66X_1 (7U) 343 #define IPC_C66X_2 (8U) 344 #define IPC_C7X_1 (9U) 345 #define IPC_MPU1_1 (10U) 346 #define IPC_MAX_PROCS (11U) 350 #define CDD_IPC_CORE_ID_MAX (11U) 352 #define IPC_MAILBOX_CLUSTER_CNT (12U) 391 #define CDD_IPC_NEW_MSG_NTFY_FXN Cdd_IpcNewMessageNotify 393 #if (STD_ON == CDD_IPC_ANNOUNCE_API) 407 #define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN Cdd_IpcNewCtrlMessageNotify 437 ISR( Cdd_IpcIrqMbxFromMcu_20 );
439 ISR( Cdd_IpcIrqMbxFromMcu_21 );
#define CDD_IPC_VERTIO_OBJECT_SIZE
Definition: Cdd_IpcCfg.h:295
const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT]
ISR(Cdd_IpcIrqMbxFromMcu_20)
A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is...
#define IPC_MAX_PROCS
Definition: Cdd_IpcCfg.h:346
void Cdd_IpcNewMessageNotify(uint32 comId)
New Message notification function.
Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS]
const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS]
Processor IDs to name mapping for all processor in Jacinto7.
#define IPC_MAILBOX_CLUSTER_CNT
Definition: Cdd_IpcCfg.h:352
void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId)
New Control Message notification function.
uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE]
Communication Channels configured.