100 #define ETH_ISR_VOID (0x00U) 102 #define ETH_ISR_CAT1 (0x01U) 104 #define ETH_ISR_CAT2 (0x02U) 117 #define ETH_START_SEC_ISR_CODE 118 #include "Eth_MemMap.h" 138 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 140 #elif (ETH_ISR_TYPE == ETH_ISR_CAT2) 163 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 165 #elif (ETH_ISR_TYPE == ETH_ISR_CAT2) 169 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 175 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 199 #if (STD_ON == ETH_ENABLE_MII_API) 200 #if (ETH_ISR_TYPE == ETH_ISR_CAT1 || ETH_ISR_TYPE == ETH_ISR_VOID) 202 #elif (ETH_ISR_TYPE == ETH_ISR_CAT2) 207 #define ETH_STOP_SEC_ISR_CODE 208 #include "Eth_MemMap.h" void Eth_TxIrqHdlr_0(void)
ISR for frame transmission interrupts of the indexed controller.
ISR(Cdd_IpcIrqMbxFromMcu_20)
A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is...
void Eth_RxIrqHdlr_0(void)
ISR for frame reception interrupts of the indexed controller.
void Eth_MdioIrqHdlr_0(void)
ISR for MDIO interrupts of the indexed controller.
void Eth_RxIrqPacingHdlr_0(void)
void Eth_TxIrqPacingHdlr_0(void)