PDK API Guide for J721E
Macros | Functions
csl_psilcfg.h File Reference
CSL-FL » PSIL Config CSL-FL

Introduction

This is the CSL header file for the Packet Streaming Interface Link (PSI-L) configuration CSL-FL.

Go to the source code of this file.

PSI-L Configuration Registers

PSI-L Configuration Registers

#define CSL_PSILCFG_REG_PEER_THREAD_ID   ((uint32_t) 0U)
 
#define CSL_PSILCFG_REG_PEER_CREDIT   ((uint32_t) 0x001U)
 
#define CSL_PSILCFG_REG_ENABLE   ((uint32_t) 0x002U)
 
#define CSL_PSILCFG_REG_CAPABILITIES   ((uint32_t) 0x040U)
 
#define CSL_PSILCFG_REG_STATIC_TR   ((uint32_t) 0x400U)
 
#define CSL_PSILCFG_REG_STATIC_TR_Z   ((uint32_t) 0x401U)
 
#define CSL_PSILCFG_REG_BYTE_COUNT   ((uint32_t) 0x404U)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG   ((uint32_t) 0x405U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0   ((uint32_t) 0x406U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1   ((uint32_t) 0x407U)
 
#define CSL_PSILCFG_REG_RT_ENABLE   ((uint32_t) 0x408U)
 
#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E(N)   ((uint32_t)0x4000U + (uint32_t)(N))
 
typedef uint32_t CSL_PsilCfgReg
 

Macros

#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_SHIFT   (0)
 
#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_MASK   ((uint32_t)0xFFFFU<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_ID_SHIFT)
 
#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_SHIFT   (24U)
 
#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_MASK   ((uint32_t)0x1FU<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_WIDTH_SHIFT)
 
#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_SHIFT   (29U)
 
#define CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_MASK   ((uint32_t)0x7U<<CSL_PSILCFG_REG_PEER_THREAD_ID_THREAD_PRI_SHIFT)
 
#define CSL_PSILCFG_REG_PEER_CREDIT_CNT_SHIFT   (0)
 
#define CSL_PSILCFG_REG_PEER_CREDIT_CNT_MASK   ((uint32_t)0xFFU<<CSL_PSILCFG_REG_PEER_CREDIT_CNT_SHIFT)
 
#define CSL_PSILCFG_REG_ENABLE_ENABLE_SHIFT   (31U)
 
#define CSL_PSILCFG_REG_ENABLE_ENABLE_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_ENABLE_ENABLE_SHIFT)
 
#define CSL_PSILCFG_REG_ENABLE_TEARDOWN_SHIFT   (30U)
 
#define CSL_PSILCFG_REG_ENABLE_TEARDOWN_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_ENABLE_TEARDOWN_SHIFT)
 
#define CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_SHIFT   (0)
 
#define CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_MASK   ((uint32_t)0xFFU<<CSL_PSILCFG_REG_CAPABILITIES_CREDIT_CNT_SHIFT)
 
#define CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_SHIFT   (24U)
 
#define CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_MASK   ((uint32_t)0x1FU<<CSL_PSILCFG_REG_CAPABILITIES_THREAD_WIDTH_SHIFT)
 
#define CSL_PSILCFG_REG_STATIC_TR_X_SHIFT   (24U)
 
#define CSL_PSILCFG_REG_STATIC_TR_X_MASK   (((uint32_t)0x0007U) << CSL_PSILCFG_REG_STATIC_TR_X_SHIFT)
 
#define CSL_PSILCFG_REG_STATIC_TR_Y_SHIFT   (0U)
 
#define CSL_PSILCFG_REG_STATIC_TR_Y_MASK   (((uint32_t)0x0FFFU) << CSL_PSILCFG_REG_STATIC_TR_Y_SHIFT)
 
#define CSL_PSILCFG_REG_STATIC_TR_Z_SHIFT   (0U)
 
#define CSL_PSILCFG_REG_STATIC_TR_Z_MASK   (((uint32_t)0x0FFFU) << CSL_PSILCFG_REG_STATIC_TR_Z_SHIFT)
 
#define CSL_PSILCFG_REG_RT_ENABLE_IDLE_SHIFT   (1U)
 
#define CSL_PSILCFG_REG_RT_ENABLE_IDLE_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_IDLE_SHIFT)
 
#define CSL_PSILCFG_REG_RT_ENABLE_FLUSH_SHIFT   (28U)
 
#define CSL_PSILCFG_REG_RT_ENABLE_FLUSH_MASK   ((uint32_t)0x01U << CSL_PSILCFG_REG_RT_ENABLE_FLUSH_SHIFT)
 
#define CSL_PSILCFG_REG_RT_ENABLE_PAUSE_SHIFT   (29U)
 
#define CSL_PSILCFG_REG_RT_ENABLE_PAUSE_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_PAUSE_SHIFT)
 
#define CSL_PSILCFG_REG_RT_ENABLE_TDOWN_SHIFT   (30U)
 
#define CSL_PSILCFG_REG_RT_ENABLE_TDOWN_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_TDOWN_SHIFT)
 
#define CSL_PSILCFG_REG_RT_ENABLE_ENABLE_SHIFT   (31U)
 
#define CSL_PSILCFG_REG_RT_ENABLE_ENABLE_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_RT_ENABLE_ENABLE_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_SHIFT   (0U)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_MASK   ((uint32_t)0x0FFFFU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_MASK_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_SHIFT   (16U)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_FIRST_SLOT_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_SHIFT   (20U)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_LAST_SLOT_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_SHIFT   (30U)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_DMA_REQ_RESET_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_SHIFT   (31U)
 
#define CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_MASK   ((uint32_t)0x01U<<CSL_PSILCFG_REG_AASRC_FIFO_CFG_GROUP_MODE_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_SHIFT   (0U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY0_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_SHIFT   (4U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY1_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_SHIFT   (8U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY2_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_SHIFT   (12U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY3_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_SHIFT   (16U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY4_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_SHIFT   (20U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY5_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_SHIFT   (24U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY6_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_SHIFT   (28U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE0_ENTRY7_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_SHIFT   (0U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY8_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_SHIFT   (4U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY9_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_SHIFT   (8U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY10_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_SHIFT   (12U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY11_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_SHIFT   (16U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY12_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_SHIFT   (20U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY13_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_SHIFT   (24U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY14_SHIFT)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_SHIFT   (28U)
 
#define CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_MASK   ((uint32_t)0x0FU<<CSL_PSILCFG_REG_AASRC_ORDER_TABLE1_ENTRY15_SHIFT)
 
#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_SHIFT   (0U)
 
#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_MASK   ((uint32_t)0xFFFFU<<CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_INDEX_SHIFT)
 
#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_SHIFT   (31U)
 
#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_MASK   ((uint32_t)0x1U<<CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_SHIFT)
 
#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_PULSE   ((uint32_t) 0U)
 
#define CSL_PSILCFG_REG_LOCAL_TO_GLOBAL_MAPPING_E_TYPE_RISING_EDGE   ((uint32_t) 1U)
 

Functions

uint32_t CSL_psilcfgGetRevision (const CSL_psilcfgRegs *pRegs)
 Return revision of the PSILCFG module. More...
 
bool CSL_psilcfgWrite (const CSL_psilcfgRegs *pRegs, uint32_t threadId, uint32_t regId, uint32_t data)
 Write a value to a PSI-L periperal using the PSI-L configuration proxy. More...
 
bool CSL_psilcfgRead (const CSL_psilcfgRegs *pRegs, uint32_t threadId, uint32_t regId, uint32_t *pData)
 Read a value from a PSI-L periperal using the PSI-L configuration proxy. More...
 
bool CSL_psilcfgSetThreadEnable (const CSL_psilcfgRegs *pRegs, uint32_t threadId, bool bEnable)
 Enable or disable a thread. More...
 
bool CSL_psilcfgSetThreadRealtimeEnable (const CSL_psilcfgRegs *pRegs, uint32_t threadId, bool bEnable)
 Enable or disable a thread via the realtime register. More...
 
bool CSL_psilcfgTeardownThread (const CSL_psilcfgRegs *pRegs, uint32_t threadId)
 Teardown a thread. More...
 
bool CSL_psilcfgClrTeardown (const CSL_psilcfgRegs *pRegs, uint32_t threadId)
 Clear a thread's teardown and flush bits. More...
 
bool CSL_psilcfgFlushThread (const CSL_psilcfgRegs *pRegs, uint32_t threadId)
 Flush data from a destination thread. More...
 
bool CSL_psilcfgSetThreadPause (const CSL_psilcfgRegs *pRegs, uint32_t threadId, bool bPause)
 Pause or un-pause a thread. More...
 
bool CSL_psilcfgCreateRoute (const CSL_psilcfgRegs *pRegs, uint32_t srcThreadId, uint32_t dstThreadId)
 Create a route through the PSI-L switch. More...
 
bool CSL_psilcfgCreateLink (const CSL_psilcfgRegs *pRegs, uint32_t srcThreadId, uint32_t dstThreadId)
 Create a link through the PSI-L switch. More...
 
bool CSL_psilcfgIsThreadIdle (const CSL_psilcfgRegs *pRegs, uint32_t threadId)
 Determine if a disabled or paused thread is idle. More...