81 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U) 84 #define ENETPHY_BIT(n) (1U << (n)) 87 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U) 90 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0])) 104 #define ENETPHY_SOK (CSL_PASS) 107 #define ENETPHY_EFAIL (CSL_EFAIL) 110 #define ENETPHY_EBADARGS (CSL_EBADARGS) 113 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS) 116 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT) 119 #define ENETPHY_EALLOC (CSL_EALLOC) 122 #define ENETPHY_EPERM (CSL_EALLOC - 4) 125 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5) 139 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1) 142 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2) 145 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3) 148 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4) 151 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5) 154 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6) 157 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \ 158 ENETPHY_LINK_CAP_FD10) 161 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \ 162 ENETPHY_LINK_CAP_FD100) 165 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \ 166 ENETPHY_LINK_CAP_FD1000) 169 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \ 170 ENETPHY_LINK_CAP_FD10 | \ 171 ENETPHY_LINK_CAP_HD100 | \ 172 ENETPHY_LINK_CAP_FD100 | \ 173 ENETPHY_LINK_CAP_HD1000 | \ 174 ENETPHY_LINK_CAP_FD1000) 179 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U) 182 #define ENETPHY_FSM_TICK_PERIOD_MS (100U) 185 #define ENETPHY_INVALID_PHYADDR (~0U) 194 typedef enum EnetPhy_Magic_e
206 typedef enum EnetPhy_Mii_e
230 typedef enum EnetPhy_Speed_e
248 typedef enum EnetPhy_Duplexity_e
263 typedef struct EnetPhy_Version_s
278 typedef enum EnetPhy_LinkStatus_e
296 typedef struct EnetPhy_LinkCfg_s
308 typedef struct EnetPhy_FsmTimeoutCfg_s
335 typedef struct EnetPhy_Cfg_s
379 typedef struct EnetPhy_Mdio_s
393 int32_t (*isAlive)(uint32_t phyAddr,
409 int32_t (*isLinked)(uint32_t phyAddr,
426 int32_t (*readC22)(uint32_t group,
445 int32_t (*writeC22)(uint32_t group,
465 int32_t (*readC45)(uint32_t group,
486 int32_t (*writeC45)(uint32_t group,
507 typedef enum EnetPhy_FsmState_e
543 typedef struct EnetPhy_State_s
594 typedef struct EnetPhy_Obj_s
672 const void *extendedCfg,
673 uint32_t extendedCfgSize);
695 uint32_t macPortCaps,
uint32_t addr
Definition: enetphy.h:621
bool loopbackEn
Definition: enetphy.h:582
uint32_t group
Definition: enetphy.h:618
Definition: enetphy.h:242
uint32_t phyAddr
Definition: enetphy.h:341
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks)
Definition: enetphy.h:320
Definition: enetphy.h:287
uint32_t phyGroup
Definition: enetphy.h:338
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:507
uint32_t extendedCfgSize
Definition: enetphy.h:373
bool enableNway
Definition: enetphy.h:567
MII interface.
Definition: enetphy.h:209
bool mdixEn
Definition: enetphy.h:347
PHY State-Machine time-out values.
Definition: enetphy.h:308
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:278
Definition: enetphy.h:251
struct EnetPhy_Drv_s * EnetPhyDrv_Handle
PHY specific driver handle.
Definition: enetphy.h:502
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
RGMII interface.
Definition: enetphy.h:218
bool needsNwayCfg
Definition: enetphy.h:573
int32_t EnetPhy_rmwReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
bool masterMode
Definition: enetphy.h:358
Definition: enetphy.h:257
PHY configuration parameters.
Definition: enetphy.h:335
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:612
bool skipExtendedCfg
Definition: enetphy.h:364
Definition: enetphy.h:284
bool needsManualCfg
Definition: enetphy.h:570
uint32_t findingStateTicks
FINDING state timeout (in ticks)
Definition: enetphy.h:311
Definition: enetphy.h:239
FINDING state.
Definition: enetphy.h:513
uint32_t timeout
Definition: enetphy.h:558
SGMII interface.
Definition: enetphy.h:221
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
Open the PHY driver.
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
bool needsMdixSwitch
Definition: enetphy.h:585
int32_t EnetPhy_readExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY extended register.
uint32_t revision
Definition: enetphy.h:272
EnetPhyDrv_Handle hDrv
Definition: enetphy.h:627
int32_t EnetPhy_readReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY register.
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
Definition: enetphy.h:200
bool extClkSource
Definition: enetphy.h:361
PHY version (ID).
Definition: enetphy.h:263
EnetPhy_State state
Definition: enetphy.h:615
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:525
uint32_t residenceTime
Definition: enetphy.h:561
bool enableMdix
Definition: enetphy.h:588
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks)
Definition: enetphy.h:329
MDIO driver.
Definition: enetphy.h:379
INIT state.
Definition: enetphy.h:510
EnetPhy_Duplexity duplexity
Definition: enetphy.h:302
QSGMII interface.
Definition: enetphy.h:224
RESET_WAIT state.
Definition: enetphy.h:516
LINKED state.
Definition: enetphy.h:534
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_Speed speed
Definition: enetphy.h:299
uint32_t linkCaps
Definition: enetphy.h:576
bool isStrapped
Definition: enetphy.h:352
Link speed and duplexity configuration.
Definition: enetphy.h:296
uint32_t model
Definition: enetphy.h:269
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks)
Definition: enetphy.h:314
FOUND state.
Definition: enetphy.h:522
EnetPhy_Mii mii
Definition: enetphy.h:603
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:367
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
EnetPhy_Speed speed
Definition: enetphy.h:552
bool isNwayCapable
Definition: enetphy.h:564
Definition: enetphy.h:197
ENABLE state.
Definition: enetphy.h:519
bool fsmStateChanged
Definition: enetphy.h:549
EnetPhy_Magic magic
Definition: enetphy.h:630
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:179
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:609
RMII interface.
Definition: enetphy.h:212
GMII interface.
Definition: enetphy.h:215
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:194
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks)
Definition: enetphy.h:317
uint32_t phyLinkCaps
Definition: enetphy.h:579
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
Definition: enetphy.h:233
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:248
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
uint32_t oui
Definition: enetphy.h:266
PHY driver object.
Definition: enetphy.h:594
uint32_t macCaps
Definition: enetphy.h:606
PHY driver FSM state.
Definition: enetphy.h:543
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks)
Definition: enetphy.h:323
bool loopbackEn
Definition: enetphy.h:355
This file contains the Register Desciptions for CSL types.
LINK_WAIT state.
Definition: enetphy.h:531
int32_t EnetPhy_writeReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY register.
void * mdioArgs
Definition: enetphy.h:633
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:230
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:497
uint32_t nwayCaps
Definition: enetphy.h:344
LOOPBACK state.
Definition: enetphy.h:537
uint32_t reqLinkCaps
Definition: enetphy.h:624
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:641
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks)
Definition: enetphy.h:326
EnetPhy_FsmState fsmState
Definition: enetphy.h:546
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:528
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
int32_t EnetPhy_writeExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY extended register.
Definition: enetphy.h:281
Definition: enetphy.h:254
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:206
uint16_t version
Definition: tisci_core.h:443
Definition: enetphy.h:290
EnetPhy_Cfg phyCfg
Definition: enetphy.h:600
EnetPhy_Duplexity duplexity
Definition: enetphy.h:555
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:597
Definition: enetphy.h:236