CSIRX_DphyLaneControl Struct Reference

Detailed Description

DPHY lane control for data and clock lanes enables and resets

Data Fields
uint8_t	dlEnable [CSIRX_MAX_NUM_OF_STREAMS]
uint8_t	clEnable
uint8_t	dlReset [CSIRX_MAX_NUM_OF_STREAMS]
uint8_t	clReset

Field Documentation

dlEnable

uint8_t CSIRX_DphyLaneControl::dlEnable[CSIRX_MAX_NUM_OF_STREAMS]

DPHY data lane Enable

clEnable

uint8_t CSIRX_DphyLaneControl::clEnable

DPHY Clock lane Enable

dlReset

uint8_t CSIRX_DphyLaneControl::dlReset[CSIRX_MAX_NUM_OF_STREAMS]

DPHY data lane Reset

clReset

uint8_t CSIRX_DphyLaneControl::clReset

DPHY Clock lane Reset