CSIRX_StreamCfg Struct Reference

Detailed Description

Primary CSI2 Slave Controller Data pixel outputs configuration. This register is used to configure the output mode. It is also used to set up some Stream FIFO related settings.

Data Fields
uint16_t	fifoFill
uint8_t	bppBypass
uint8_t	fifoMode
uint8_t	numPixels
uint8_t	lsLeMode
uint8_t	interfaceMode

Field Documentation

fifoFill

uint16_t CSIRX_StreamCfg::fifoFill

Set the FIFO_FILL_LEVEL which is used to hold data in the FIFO until this level is reached before allow data to be pulled. This setting is only used when FifoMode is set for Large Buffer operation

bppBypass

uint8_t CSIRX_StreamCfg::bppBypass

Force unpacking of any Data type as selected RAW type. 0 - No bypass 1 - unpack as RAW6 2 - unpack as RAW7 3 - unpack as RAW8 4 - unpack as RAW10 5 - unpack as RAW12 6 - unpack as RAW14 7 - unpack as RAW16

fifoMode

uint8_t CSIRX_StreamCfg::fifoMode

Stream FIFO configuration, which must be set in accordance to FIFO sizing, flow control and the relationship between the link and pixel interface data rates. Refer to Use Case descriptions for further guidance on FIFO sizing and valid stream configuration options. 00: Full Line Buffer. Hold data in FIFO until CRC check completes. 01: Large Buffer (Fill Level Controlled). Hold data in FIFO until FIFO_FILL_LEVEL is reached. 1x: Short Buffer. When pixel output data rate can match link data rate, a small buffer can be used to accommodate CDC, pixel data packing, and data rate matching

numPixels

uint8_t CSIRX_StreamCfg::numPixels

Number of pixels to output from the stream. Valid values are 1, 2, 4 and 8. The width of the pixel interface and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle. Default will be 1 pixel per clock. 00 -> 1 pixel per clock 01 -> 2 pixels per clock 10 -> 4 pixels per clock 11 -> 8 pixels per clock (Reserved)

lsLeMode

uint8_t CSIRX_StreamCfg::lsLeMode

Enable LS/LE control of HYSNC_VALID output. By default, LS and LE short packets are not required and HYSC_VALID will be generated from the start and end of payload data.

interfaceMode

uint8_t CSIRX_StreamCfg::interfaceMode

Select the output configuration. Pixel = 0 (default) Packed = 1