PDK API Guide for J721E
Data Fields
CSITX_DphyConfig1 Struct Reference
CSL-FL » CSITX CSL-FL » CSITX Dynamic Data Structures

Detailed Description

Configuration of DPHY (CFG1)

Data Fields

bool forceStopModeLn0
 
bool forceStopModeLn1
 
bool forceStopModeLn2
 
bool forceStopModeLn3
 
bool diffInvertLn0
 
bool diffInvertLn1
 
bool diffInvertLn2
 
bool diffInvertLn3
 
bool diffInvertClock
 

Field Documentation

◆ forceStopModeLn0

bool CSITX_DphyConfig1::forceStopModeLn0

D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 0.

◆ forceStopModeLn1

bool CSITX_DphyConfig1::forceStopModeLn1

D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 1.

◆ forceStopModeLn2

bool CSITX_DphyConfig1::forceStopModeLn2

D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 2.

◆ forceStopModeLn3

bool CSITX_DphyConfig1::forceStopModeLn3

D-PHY Transmitter FORCE_STOP_MODE TX Data Lane 3.

◆ diffInvertLn0

bool CSITX_DphyConfig1::diffInvertLn0

D-PHY Transmitter invert differential pair on TX Data Lane 0.

◆ diffInvertLn1

bool CSITX_DphyConfig1::diffInvertLn1

D-PHY Transmitter invert differential pair on TX Data Lane 1.

◆ diffInvertLn2

bool CSITX_DphyConfig1::diffInvertLn2

D-PHY Transmitter invert differential pair on TX Data Lane 2.

◆ diffInvertLn3

bool CSITX_DphyConfig1::diffInvertLn3

D-PHY Transmitter invert differential pair on TX Data Lane 3.

◆ diffInvertClock

bool CSITX_DphyConfig1::diffInvertClock

D-PHY Transmitter invert differential pair on TX Clock Lane.