PDK API Guide for J721E
CSL_CPSW_PORTSTAT Struct Reference

Detailed Description

Holds Port Statistics Enable register contents.

Data Fields

Uint32 p0StatEnable
 
Uint32 p1StatEnable
 
Uint32 p2StatEnable
 
Uint32 p3StatEnable
 
Uint32 p4StatEnable
 
Uint32 p5StatEnable
 
Uint32 p6StatEnable
 
Uint32 p7StatEnable
 
Uint32 p8StatEnable
 

Field Documentation

◆ p0StatEnable

Uint32 CSL_CPSW_PORTSTAT::p0StatEnable

Port 0 Statistics Enable bit

◆ p1StatEnable

Uint32 CSL_CPSW_PORTSTAT::p1StatEnable

Port 1 Statistics Enable bit

◆ p2StatEnable

Uint32 CSL_CPSW_PORTSTAT::p2StatEnable

Port 2 Statistics Enable bit

◆ p3StatEnable

Uint32 CSL_CPSW_PORTSTAT::p3StatEnable

Port 3 Statistics Enable bit

◆ p4StatEnable

Uint32 CSL_CPSW_PORTSTAT::p4StatEnable

Port 4 Statistics Enable bit

◆ p5StatEnable

Uint32 CSL_CPSW_PORTSTAT::p5StatEnable

Port 5 Statistics Enable bit

◆ p6StatEnable

Uint32 CSL_CPSW_PORTSTAT::p6StatEnable

Port 6 Statistics Enable bit

◆ p7StatEnable

Uint32 CSL_CPSW_PORTSTAT::p7StatEnable

Port 7 Statistics Enable bit

◆ p8StatEnable

Uint32 CSL_CPSW_PORTSTAT::p8StatEnable

Port 8 Statistics Enable bit