Detailed Description

Holds Port Time Sync Control register contents.

Data Fields
Uint32	tsRxAnnexDEnable

Uint32	tsRxAnnexEEnable

Uint32	tsRxAnnexFEnable

Uint32	tsRxVlanLType1Enable

Uint32	tsRxVlanLType2Enable

Uint32	tsTxAnnexDEnable

Uint32	tsTxAnnexEEnable

Uint32	tsTxAnnexFEnable

Uint32	tsTxVlanLType1Enable

Uint32	tsTxVlanLType2Enable

Uint32	tsTxHostEnable

Uint32	tsLType2Enable

Uint32	tsMsgTypeEnable

Field Documentation

◆ tsRxAnnexDEnable

Uint32 CSL_CPSW_TSCNTL::tsRxAnnexDEnable

Port Time sync receive Annex D enable bit

◆ tsRxAnnexEEnable

Uint32 CSL_CPSW_TSCNTL::tsRxAnnexEEnable

Port Time sync receive Annex E enable bit

◆ tsRxAnnexFEnable

Uint32 CSL_CPSW_TSCNTL::tsRxAnnexFEnable

Port Time sync receive Annex F enable bit

◆ tsRxVlanLType1Enable

Uint32 CSL_CPSW_TSCNTL::tsRxVlanLType1Enable

Port Time sync receive VLAN LTYPE 1 enable bit

◆ tsRxVlanLType2Enable

Uint32 CSL_CPSW_TSCNTL::tsRxVlanLType2Enable

Port Time sync receive VLAN LTYPE 2 enable bit

◆ tsTxAnnexDEnable

Uint32 CSL_CPSW_TSCNTL::tsTxAnnexDEnable

Port Time sync transmit Annex D enable bit

◆ tsTxAnnexEEnable

Uint32 CSL_CPSW_TSCNTL::tsTxAnnexEEnable

Port Time sync transmit Annex E enable bit

◆ tsTxAnnexFEnable

Uint32 CSL_CPSW_TSCNTL::tsTxAnnexFEnable

Port Time sync transmit Annex F enable bit

◆ tsTxVlanLType1Enable

Uint32 CSL_CPSW_TSCNTL::tsTxVlanLType1Enable

Port Time sync transmit VLAN LTYPE 1 enable bit

◆ tsTxVlanLType2Enable

Uint32 CSL_CPSW_TSCNTL::tsTxVlanLType2Enable

Port Time sync transmit VLAN LTYPE 2 enable bit

◆ tsTxHostEnable

Uint32 CSL_CPSW_TSCNTL::tsTxHostEnable

Port Time sync transmit host timestamp enable bit

◆ tsLType2Enable

Uint32 CSL_CPSW_TSCNTL::tsLType2Enable

Port Time sync transmit and receive LType2 enable bit

◆ tsMsgTypeEnable

Uint32 CSL_CPSW_TSCNTL::tsMsgTypeEnable

Port Time sync message type enable bits