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PDK API Guide for J721E
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Holds Port Time Sync Configuration contents.
Data Fields | |
Uint32 | tsRxAnnexDEnable |
Uint32 | tsRxAnnexEEnable |
Uint32 | tsRxAnnexFEnable |
Uint32 | tsRxVlanLType1Enable |
Uint32 | tsRxVlanLType2Enable |
Uint32 | tsTxAnnexDEnable |
Uint32 | tsTxAnnexEEnable |
Uint32 | tsTxAnnexFEnable |
Uint32 | tsTxVlanLType1Enable |
Uint32 | tsTxVlanLType2Enable |
Uint32 | tsTxHostEnable |
Uint32 | tsLType2Enable |
Uint32 | tsMsgTypeEnable |
Uint32 | tsUniEnable |
Uint32 | ts107Enable |
Uint32 | ts129Enable |
Uint32 | ts130Enable |
Uint32 | ts131Enable |
Uint32 | ts132Enable |
Uint32 | ts319Enable |
Uint32 | ts320Enable |
Uint32 | tsMcastTypeEnable |
Uint32 | tsTTLNonzeroEnable |
Uint32 | tsLType1 |
Uint32 | tsLType2 |
Uint32 | tsVlanLType1 |
Uint32 | tsVlanLType2 |
Uint32 | tsSeqIdOffset |
Uint32 | tsDomainOffset |
Uint32 CSL_CPSW_TSCONFIG::tsRxAnnexDEnable |
Port Time sync receive Annex D enable
Uint32 CSL_CPSW_TSCONFIG::tsRxAnnexEEnable |
Port Time sync receive Annex E enable
Uint32 CSL_CPSW_TSCONFIG::tsRxAnnexFEnable |
Port Time sync receive Annex F enable
Uint32 CSL_CPSW_TSCONFIG::tsRxVlanLType1Enable |
Port Time sync receive VLAN LTYPE 1 enable
Uint32 CSL_CPSW_TSCONFIG::tsRxVlanLType2Enable |
Port Time sync receive VLAN LTYPE 2 enable
Uint32 CSL_CPSW_TSCONFIG::tsTxAnnexDEnable |
Port Time sync transmit Annex D enable
Uint32 CSL_CPSW_TSCONFIG::tsTxAnnexEEnable |
Port Time sync transmit Annex E enable
Uint32 CSL_CPSW_TSCONFIG::tsTxAnnexFEnable |
Port Time sync transmit Annex F enable
Uint32 CSL_CPSW_TSCONFIG::tsTxVlanLType1Enable |
Port Time sync transmit VLAN LTYPE 1 enable
Uint32 CSL_CPSW_TSCONFIG::tsTxVlanLType2Enable |
Port Time sync transmit VLAN LTYPE 2 enable
Uint32 CSL_CPSW_TSCONFIG::tsTxHostEnable |
Port Time sync transmit host timestamp enable
Uint32 CSL_CPSW_TSCONFIG::tsLType2Enable |
Port Time sync transmit and receive LType2 enable
Uint32 CSL_CPSW_TSCONFIG::tsMsgTypeEnable |
Port Time sync message type enable bitmap
Uint32 CSL_CPSW_TSCONFIG::tsUniEnable |
Port Time Sync Unicast IP message enable 1: all IP address valid 0: perform multicast address check, only multicast addresses which are enabled are valid
Uint32 CSL_CPSW_TSCONFIG::ts107Enable |
Port Time Sync Destination IP Address 107 enable IPv4: 224.0.0.107 IPv6: FF0M:0:0:0:0:0:0:006B
Uint32 CSL_CPSW_TSCONFIG::ts129Enable |
Port Time Sync Destination IP Address 129 enable IPv4: 224.0.0.129 IPv6: FF0M:0:0:0:0:0:0:0181
Uint32 CSL_CPSW_TSCONFIG::ts130Enable |
Port Time Sync Destination IP Address 130 enable IPv4: 224.0.0.130 IPv6: FF0M:0:0:0:0:0:0:0182
Uint32 CSL_CPSW_TSCONFIG::ts131Enable |
Port Time Sync Destination IP Address 131 enable IPv4: 224.0.0.130 IPv6: FF0M:0:0:0:0:0:0:0183
Uint32 CSL_CPSW_TSCONFIG::ts132Enable |
Port Time Sync Destination IP Address 132 enable IPv4: 224.0.0.131 IPv6: FF0M:0:0:0:0:0:0:0184
Uint32 CSL_CPSW_TSCONFIG::ts319Enable |
Port Time Sync UDP Destination Port Number 319 enable
Uint32 CSL_CPSW_TSCONFIG::ts320Enable |
Port Time Sync UDP Destination Port Number 320 enable
Uint32 CSL_CPSW_TSCONFIG::tsMcastTypeEnable |
Port Time sync message IPv6 Multicast Address FF0M enable
Uint32 CSL_CPSW_TSCONFIG::tsTTLNonzeroEnable |
Port Time Sync Time to Live Non-zero enable
Uint32 CSL_CPSW_TSCONFIG::tsLType1 |
Port Time Sync LTYPE1 value for Annex F packets
Uint32 CSL_CPSW_TSCONFIG::tsLType2 |
Port Time Sync LTYPE2 value for Annex F packets
Uint32 CSL_CPSW_TSCONFIG::tsVlanLType1 |
Port Time Sync VLAN LTYPE1 value for both Tx and Rx packets
Uint32 CSL_CPSW_TSCONFIG::tsVlanLType2 |
Port Time Sync VLAN LTYPE2 value for both Tx and Rx packets
Uint32 CSL_CPSW_TSCONFIG::tsSeqIdOffset |
Port Time Sync Sequence ID field byte Offset in PTP message
Uint32 CSL_CPSW_TSCONFIG::tsDomainOffset |
Port Time Sync Domain field byte Offset in PTP message