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PDK API Guide for J721E
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Holds the CPTS control register info.
Data Fields | |
uint32_t | cptsEn |
uint32_t | intTest |
uint32_t | tsCompPolarity |
uint32_t | tstampEn |
uint32_t | seqEn |
uint32_t | ts64bMode |
uint32_t | tsCompToggle |
uint32_t | tsHwPushEn [8] |
CSL_CPTS_TS_OUTPUT_BIT | tsOutputBitSel |
uint32_t | tsDisableRxEvents |
uint32_t | tsGenfClrEn |
uint32_t CSL_CPTS_CONTROL::cptsEn |
Time Sync Enable: When disabled (cleared to zero), the RCLK domain is held in reset.
uint32_t CSL_CPTS_CONTROL::intTest |
Interrupt Test: When set, this bit allows the raw interrupt to be written to facilitate interrupt test.
uint32_t CSL_CPTS_CONTROL::tsCompPolarity |
TS_COMP Polarity: 0 - TS_COMP is asserted low; 1: TS_COMP is asserted high
uint32_t CSL_CPTS_CONTROL::tstampEn |
Host Receive Timestamp Enable: When set, Timestamps enabled on received packets to host
uint32_t CSL_CPTS_CONTROL::seqEn |
Sequence Enable: 0: The timestamp value increments with the selected RFTCLK 1: The timestamp for received packets is the sequence number of the received packet
uint32_t CSL_CPTS_CONTROL::ts64bMode |
64-bit mode: 0: The timestamp is 32-bits with the upper 32-bits forced to zero. 1: The timestamp is 64-bits.
uint32_t CSL_CPTS_CONTROL::tsCompToggle |
TS_COMP Toggle mode - 0: TS_COMP is in non-toggle mode; 1: TS_COMP is in toggle mode
uint32_t CSL_CPTS_CONTROL::tsHwPushEn[8] |
Hardware push 1-8 enable
CSL_CPTS_TS_OUTPUT_BIT CSL_CPTS_CONTROL::tsOutputBitSel |
TS_SYNC output timestamp counter bit select
uint32_t CSL_CPTS_CONTROL::tsDisableRxEvents |
Disable Timestamp Ethernet receive events: 0: Receive events are enabled 1: Receive events are disabled
uint32_t CSL_CPTS_CONTROL::tsGenfClrEn |
GENF (and ESTF) clear enable: 0: A TS_GENFn (or TS_ESTFn) output is not cleared when the associated ts_genf_length[31:0] (or ts_estf_length[31:0]) is cleared to zero 1: A TS_GENFn (or TS_ESTFn) output is cleared when the associated ts_genf_length[31:0] (or ts_estf_length[31:0]) is cleared to zero