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PDK API Guide for J721E
|
Data Fields | |
| volatile uint32_t | RTIGCTRL |
| volatile uint32_t | RTITBCTRL |
| volatile uint32_t | RTICAPCTRL |
| volatile uint32_t | RTICOMPCTRL |
| volatile uint32_t | RTIFRC0 |
| volatile uint32_t | RTIUC0 |
| volatile uint32_t | RTICPUC0 |
| volatile uint32_t | RESTRICTED1 |
| volatile uint32_t | RTICAFRC0 |
| volatile uint32_t | RTICAUC0 |
| volatile uint32_t | RESTRICTED2 [2] |
| volatile uint32_t | RTIFRC1 |
| volatile uint32_t | RTIUC1 |
| volatile uint32_t | RTICPUC1 |
| volatile uint32_t | RESTRICTED3 |
| volatile uint32_t | RTICAFRC1 |
| volatile uint32_t | RTICAUC1 |
| volatile uint32_t | RESTRICTED4 [2] |
| volatile uint32_t | RTICOMP0 |
| volatile uint32_t | RTIUDCP0 |
| volatile uint32_t | RTICOMP1 |
| volatile uint32_t | RTIUDCP1 |
| volatile uint32_t | RTICOMP2 |
| volatile uint32_t | RTIUDCP2 |
| volatile uint32_t | RTICOMP3 |
| volatile uint32_t | RTIUDCP3 |
| volatile uint32_t | RTITBLCOMP |
| volatile uint32_t | RTITBHCOMP |
| volatile uint32_t | RESTRICTED5 [2] |
| volatile uint32_t | RTISETINT |
| volatile uint32_t | RTICLEARINT |
| volatile uint32_t | RTIINTFLAG |
| volatile uint32_t | RESTRICTED6 |
| volatile uint32_t | RTIDWDCTRL |
| volatile uint32_t | RTIDWDPRLD |
| volatile uint32_t | RTIWDSTATUS |
| volatile uint32_t | RTIWDKEY |
| volatile uint32_t | RTIDWDCNTR |
| volatile uint32_t | RTIWWDRXNCTRL |
| volatile uint32_t | RTIWWDSIZECTRL |
| volatile uint32_t | RTIINTCLRENABLE |
| volatile uint32_t | RTICOMP0CLR |
| volatile uint32_t | RTICOMP1CLR |
| volatile uint32_t | RTICOMP2CLR |
| volatile uint32_t | RTICOMP3CLR |
| volatile uint32_t CSL_RTIRegs::RTIGCTRL |
Offset: 0x000
| volatile uint32_t CSL_RTIRegs::RTITBCTRL |
Offset: 0x004
| volatile uint32_t CSL_RTIRegs::RTICAPCTRL |
Offset: 0x008
| volatile uint32_t CSL_RTIRegs::RTICOMPCTRL |
Offset: 0x00C
| volatile uint32_t CSL_RTIRegs::RTIFRC0 |
Offset: 0x010
| volatile uint32_t CSL_RTIRegs::RTIUC0 |
Offset: 0x014
| volatile uint32_t CSL_RTIRegs::RTICPUC0 |
Offset: 0x018
| volatile uint32_t CSL_RTIRegs::RESTRICTED1 |
Offset: 0x01C
| volatile uint32_t CSL_RTIRegs::RTICAFRC0 |
Offset: 0x020
| volatile uint32_t CSL_RTIRegs::RTICAUC0 |
Offset: 0x024
| volatile uint32_t CSL_RTIRegs::RESTRICTED2[2] |
Offset: 0x028
| volatile uint32_t CSL_RTIRegs::RTIFRC1 |
Offset: 0x030
| volatile uint32_t CSL_RTIRegs::RTIUC1 |
Offset: 0x034
| volatile uint32_t CSL_RTIRegs::RTICPUC1 |
Offset: 0x038
| volatile uint32_t CSL_RTIRegs::RESTRICTED3 |
Offset: 0x03C
| volatile uint32_t CSL_RTIRegs::RTICAFRC1 |
Offset: 0x040
| volatile uint32_t CSL_RTIRegs::RTICAUC1 |
Offset: 0x044
| volatile uint32_t CSL_RTIRegs::RESTRICTED4[2] |
Offset: 0x048
| volatile uint32_t CSL_RTIRegs::RTICOMP0 |
Offset: 0x050
| volatile uint32_t CSL_RTIRegs::RTIUDCP0 |
Offset: 0x054
| volatile uint32_t CSL_RTIRegs::RTICOMP1 |
Offset: 0x058
| volatile uint32_t CSL_RTIRegs::RTIUDCP1 |
Offset: 0x05C
| volatile uint32_t CSL_RTIRegs::RTICOMP2 |
Offset: 0x060
| volatile uint32_t CSL_RTIRegs::RTIUDCP2 |
Offset: 0x064
| volatile uint32_t CSL_RTIRegs::RTICOMP3 |
Offset: 0x068
| volatile uint32_t CSL_RTIRegs::RTIUDCP3 |
Offset: 0x06C
| volatile uint32_t CSL_RTIRegs::RTITBLCOMP |
Offset: 0x070
| volatile uint32_t CSL_RTIRegs::RTITBHCOMP |
Offset: 0x074
| volatile uint32_t CSL_RTIRegs::RESTRICTED5[2] |
Offset: 0x078
| volatile uint32_t CSL_RTIRegs::RTISETINT |
Offset: 0x080
| volatile uint32_t CSL_RTIRegs::RTICLEARINT |
Offset: 0x084
| volatile uint32_t CSL_RTIRegs::RTIINTFLAG |
Offset: 0x088
| volatile uint32_t CSL_RTIRegs::RESTRICTED6 |
Offset: 0x08C
| volatile uint32_t CSL_RTIRegs::RTIDWDCTRL |
Offset: 0x090
| volatile uint32_t CSL_RTIRegs::RTIDWDPRLD |
Offset: 0x094
| volatile uint32_t CSL_RTIRegs::RTIWDSTATUS |
Offset: 0x098
| volatile uint32_t CSL_RTIRegs::RTIWDKEY |
Offset: 0x09C
| volatile uint32_t CSL_RTIRegs::RTIDWDCNTR |
Offset: 0x0A0
| volatile uint32_t CSL_RTIRegs::RTIWWDRXNCTRL |
Offset: 0x0A4
| volatile uint32_t CSL_RTIRegs::RTIWWDSIZECTRL |
Offset: 0x0A8
| volatile uint32_t CSL_RTIRegs::RTIINTCLRENABLE |
Offset: 0x0AC
| volatile uint32_t CSL_RTIRegs::RTICOMP0CLR |
Offset: 0x0B0
| volatile uint32_t CSL_RTIRegs::RTICOMP1CLR |
Offset: 0x0B4
| volatile uint32_t CSL_RTIRegs::RTICOMP2CLR |
Offset: 0x0B8
| volatile uint32_t CSL_RTIRegs::RTICOMP3CLR |
Offset: 0x0BC