Csirx_InstCfg Struct Reference

Detailed Description

Structure containing csirx module initialization arguments.

Data Fields
uint32_t	enableCsiv2p0Support
uint32_t	numDataLanes
uint32_t	dataLanesMap [CSIRX_CAPT_DATA_LANES_MAX]
uint32_t	enableErrbypass
uint32_t	numPixelsStrm0
uint32_t	enableStrm [CSIRX_NUM_STREAM]

Field Documentation

enableCsiv2p0Support

uint32_t Csirx_InstCfg::enableCsiv2p0Support

Enable support for CSI2 v2p0 protocol TRUE: Enables support for CSI2 v2p0 protocol FALSE: Disables support for CSI2 v2p0 protocol In v2p0, support extended for VC, up to 16 virtual channels [4-bits] and RAW16/20. Default is up to 4 virtual channels [3-bits] as per CSI2RX v1p3.

numDataLanes

uint32_t Csirx_InstCfg::numDataLanes

Number of data to be used for receiving data

dataLanesMap

uint32_t Csirx_InstCfg::dataLanesMap[CSIRX_CAPT_DATA_LANES_MAX]

physiCsirx mapping of logiCsirx data lanes dlMap[0U]: physiCsirx mapping of logiCsirx data lane 0 dlMap[1U]: physiCsirx mapping of logiCsirx data lane 1 dlMap[2U]: physiCsirx mapping of logiCsirx data lane 2 dlMap[3U]: physiCsirx mapping of logiCsirx data lane 3

enableErrbypass

uint32_t Csirx_InstCfg::enableErrbypass

Enable Error Bypass mode. Data will forwarded to stream for further even after data id, CRC, ECC errors. TRUE: Enables error bypass mode. FALSE: Disables error bypass mode.

numPixelsStrm0

uint32_t Csirx_InstCfg::numPixelsStrm0

Number of pixels to output per clock cycle from the stream0. This is stream specific configuration and this is specific to "stream0" i.e. it is common across all the channels going to DDR/Memory and all the opened driver instances for given CSI-RX port/instance.

The width of the pixel interface (32 bits) and the bits per pixel for the selected datatype will determine how many pixels can be output in a single cycle.

For example: Case 1: 2 channels - each RAW12 (bpp = 12 bits) capture, valid values are 0 (1 pixel per clock) & 1 (2 pixels per clock). 12 bits x 2 pixels per clock = 24 bits which is less than pixel interface bus width (32 bits) Case 2: 2 channels- one RAW12 (bpp = 12 bits) channel & one RGB888 (bpp = 24 bits) channel capture, valid values are 0 i.e. 1 pixel per clock (lowest of the two). RAW12: 12 bits x 2 pixels per clock = 24 bits which is less than pixel interface bus width (32 bits) RGB888: 24 bits x 1 pixel per clock = 24 bits which is less than pixel interface bus width (32 bits) Lowest of the two i.e. 1 pixel per clock is selected in this case to ensure proper operation of the module.

Valid values are 0, 1, 2. Default will be 1 pixel per clock (value of '00'). 00 -> 1 pixel per clock 01 -> 2 pixels per clock 10 -> 4 pixels per clock

enableStrm

uint32_t Csirx_InstCfg::enableStrm[CSIRX_NUM_STREAM]

Enable/Disable stream interfaces for this CSIRX instance. set enableStrm[stream_id] to 1 to enable the stream. 0 to disable the stream. stream_id could be CSIRX_CAPT_STREAM_ID/CSIRX_LPBK_STRAM_ID/ CSIRX_OTF_STREAM0_ID/CSIRX_OTF_STREAM1_ID By default, all streams are disabled. Application needs to choose which streams needs to be enabled