PDK API Guide for J721E
uart.h
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1 /*
2  * Copyright (C) 2013 - 2018 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
91 #ifndef UART_H_
92 #define UART_H_
93 
94 #ifdef __cplusplus
95 extern "C" {
96 #endif
97 
98 /* ========================================================================== */
99 /* Include Files */
100 /* ========================================================================== */
101 #include <ti/csl/cslr_uart.h>
102 
103 /* ========================================================================== */
104 /* Macros */
105 /* ========================================================================== */
106 
108 #define TX_FIFO_SIZE (64)
109 
111 #define RX_FIFO_SIZE (64)
112 
117 #define UART16x_OPER_MODE (UART_MDR1_MODE_SELECT_UART16X)
118 #define UART_SIR_OPER_MODE (UART_MDR1_MODE_SELECT_SIR)
119 #define UART16x_AUTO_BAUD_OPER_MODE (UART_MDR1_MODE_SELECT_UART16XAUTO)
120 #define UART13x_OPER_MODE (UART_MDR1_MODE_SELECT_UART13X)
121 #define UART_MIR_OPER_MODE (UART_MDR1_MODE_SELECT_MIR)
122 #define UART_FIR_OPER_MODE (UART_MDR1_MODE_SELECT_FIR)
123 #define UART_CIR_OPER_MODE (UART_MDR1_MODE_SELECT_CIR)
124 #define UART_DISABLED_MODE (UART_MDR1_MODE_SELECT_MASK)
125 
131 #define UART_TIMEOUT_COUNTER_RESET (0U)
132 #define UART_TIMEOUT_COUNTER_NO_CHANGE (1U)
133 
141 #define UART_BREAK_COND_DISABLE (UART_LCR_BREAK_EN_BREAK_EN_VALUE_0 \
142  << \
143  UART_LCR_BREAK_EN_SHIFT)
144 #define UART_BREAK_COND_ENABLE (UART_LCR_BREAK_EN_BREAK_EN_VALUE_1 \
145  << \
146  UART_LCR_BREAK_EN_SHIFT)
147 
153 #define UART_PARITY_REPR_1 (UART_LCR_PARITY_TYPE2_MASK | \
154  ( \
155  UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_0 \
156  << \
157  UART_LCR_PARITY_TYPE1_SHIFT) | \
158  UART_LCR_PARITY_EN_MASK)
159 
160 #define UART_PARITY_REPR_0 (UART_LCR_PARITY_TYPE2_MASK | \
161  ( \
162  UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_1 \
163  << \
164  UART_LCR_PARITY_TYPE1_SHIFT) | \
165  UART_LCR_PARITY_EN_MASK)
166 
167 #define UART_ODD_PARITY (( \
168  UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_0 \
169  << \
170  UART_LCR_PARITY_TYPE1_SHIFT) | \
171  UART_LCR_PARITY_EN_MASK)
172 
173 #define UART_EVEN_PARITY (( \
174  UART_LCR_PARITY_TYPE1_PARITY_TYPE1_VALUE_1 \
175  << \
176  UART_LCR_PARITY_TYPE1_SHIFT) | \
177  UART_LCR_PARITY_EN_MASK)
178 
179 #define UART_PARITY_NONE ( \
180  UART_LCR_PARITY_EN_PARITY_EN_VALUE_0 << \
181  UART_LCR_PARITY_EN_SHIFT)
182 
185 #define UART_FRAME_NUM_STB_1 (UART_LCR_NB_STOP_NB_STOP_VALUE_0 \
186  << \
187  UART_LCR_NB_STOP_SHIFT)
188 #define UART_FRAME_NUM_STB_1_5_2 (UART_LCR_NB_STOP_NB_STOP_VALUE_1 \
189  << \
190  UART_LCR_NB_STOP_SHIFT)
191 
194 #define UART_FRAME_WORD_LENGTH_5 ( \
195  UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_0)
196 #define UART_FRAME_WORD_LENGTH_6 ( \
197  UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_1)
198 #define UART_FRAME_WORD_LENGTH_7 ( \
199  UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_2)
200 #define UART_FRAME_WORD_LENGTH_8 ( \
201  UART_LCR_CHAR_LENGTH_CHAR_LENGTH_VALUE_3)
202 
212 #define UART_FCR_RX_TRIG_LVL_8 (UART_FCR_RX_FIFO_TRIG_8CHAR << \
213  UART_FCR_RX_FIFO_TRIG_SHIFT)
214 #define UART_FCR_RX_TRIG_LVL_16 (UART_FCR_RX_FIFO_TRIG_16CHAR << \
215  UART_FCR_RX_FIFO_TRIG_SHIFT)
216 #define UART_FCR_RX_TRIG_LVL_56 (UART_FCR_RX_FIFO_TRIG_56CHAR << \
217  UART_FCR_RX_FIFO_TRIG_SHIFT)
218 #define UART_FCR_RX_TRIG_LVL_60 (UART_FCR_RX_FIFO_TRIG_60CHAR << \
219  UART_FCR_RX_FIFO_TRIG_SHIFT)
220 
223 #define UART_FCR_TX_TRIG_LVL_8 (UART_FCR_TX_FIFO_TRIG_8SPACES << \
224  UART_FCR_TX_FIFO_TRIG_SHIFT)
225 #define UART_FCR_TX_TRIG_LVL_16 (UART_FCR_TX_FIFO_TRIG_16SPACES << \
226  UART_FCR_TX_FIFO_TRIG_SHIFT)
227 #define UART_FCR_TX_TRIG_LVL_32 (UART_FCR_TX_FIFO_TRIG_32SPACES << \
228  UART_FCR_TX_FIFO_TRIG_SHIFT)
229 #define UART_FCR_TX_TRIG_LVL_56 (UART_FCR_TX_FIFO_TRIG_56SPACES << \
230  UART_FCR_TX_FIFO_TRIG_SHIFT)
231 
234 #define UART_DMA_MODE_0_ENABLE ( \
235  UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_0)
236 #define UART_DMA_MODE_1_ENABLE ( \
237  UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_1)
238 #define UART_DMA_MODE_2_ENABLE ( \
239  UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_2)
240 #define UART_DMA_MODE_3_ENABLE ( \
241  UART_SCR_DMA_MODE_2_DMA_MODE_2_VALUE_3)
242 
247 #define UART_DMA_EN_PATH_FCR ( \
248  UART_SCR_DMA_MODE_CTL_DMA_MODE_CTL_VALUE_0)
249 #define UART_DMA_EN_PATH_SCR ( \
250  UART_SCR_DMA_MODE_CTL_DMA_MODE_CTL_VALUE_1)
251 
260 #define UART_INT_CTS (UART_IER_CTS_IT_MASK)
261 #define UART_INT_RTS (UART_IER_RTS_IT_MASK)
262 #define UART_INT_XOFF (UART_IER_XOFF_IT_MASK)
263 #define UART_INT_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
264 #define UART_INT_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
265 #define UART_INT_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
266 #define UART_INT_THR (UART_IER_THR_IT_MASK)
267 #define UART_INT_RHR_CTI (UART_IER_RHR_IT_MASK)
268 
269 #define UART_INT2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
270 #define UART_INT2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
271 
280 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
281 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
282 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
283 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
284 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
285 
294 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
295  << \
296  UART_IIR_IT_TYPE_SHIFT)
297 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
298  << \
299  UART_IIR_IT_TYPE_SHIFT)
300 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
301  << \
302  UART_IIR_IT_TYPE_SHIFT)
303 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
304  << \
305  UART_IIR_IT_TYPE_SHIFT)
306 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
307  << \
308  UART_IIR_IT_TYPE_SHIFT)
309 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
310  << \
311  UART_IIR_IT_TYPE_SHIFT)
312 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
313  << \
314  UART_IIR_IT_TYPE_SHIFT)
315 
317 #define UART_INT_PENDING (0U)
318 #define UART_N0_INT_PENDING (1U)
319 
328 #define UART_AUTO_CTS_ENABLE ((uint32_t) ( \
329  UART_EFR_AUTO_CTS_EN_AUTO_CTS_EN_U_VALUE_1) \
330  << \
331  (UART_EFR_AUTO_CTS_EN_SHIFT))
332 #define UART_AUTO_CTS_DISABLE ((uint32_t) ( \
333  UART_EFR_AUTO_CTS_EN_AUTO_CTS_EN_U_VALUE_0) \
334  << \
335  (UART_EFR_AUTO_CTS_EN_SHIFT))
336 
337 #define UART_AUTO_RTS_ENABLE ((uint32_t) ( \
338  UART_EFR_AUTO_RTS_EN_AUTO_RTS_EN_U_VALUE_1) \
339  << \
340  (UART_EFR_AUTO_RTS_EN_SHIFT))
341 #define UART_AUTO_RTS_DISABLE ((uint32_t) ( \
342  UART_EFR_AUTO_RTS_EN_AUTO_RTS_EN_U_VALUE_0) \
343  << \
344  (UART_EFR_AUTO_RTS_EN_SHIFT))
345 
348 #define UART_SPECIAL_CHAR_DETECT_ENABLE (UART_EFR_SPECIAL_CHAR_DETECT_MASK)
349 #define UART_SPECIAL_CHAR_DETECT_DISABLE ( \
350  UART_EFR_SPECIAL_CHAR_DETECT_SPECIAL_CHAR_DETECT_U_VALUE_0)
351 
354 #define UART_NO_SOFTWARE_FLOW_CONTROL (( \
355  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_0 \
356  << \
357  UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) \
358  | \
359  ( \
360  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_0 \
361  << \
362  UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))
363 
364 #define UART_TX_RX_XON1_XOFF1 (( \
365  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_2 \
366  << \
367  UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) \
368  | \
369  ( \
370  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_2 \
371  << \
372  UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))
373 
374 #define UART_TX_RX_XON2_XOFF2 (( \
375  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_1 \
376  << \
377  UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) \
378  | \
379  ( \
380  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_1 \
381  << \
382  UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))
383 
384 #define UART_TX_RX_XON1_XOFF1_XON2_XOFF2 (( \
385  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_3 \
386  << \
387  UART_EFR_SW_FLOW_CONTROL_TX_SHIFT) \
388  | \
389  ( \
390  UART_EFR_SW_FLOW_CONTROL_SW_FLOW_CONTROL_U_VALUE_3 \
391  << \
392  UART_EFR_SW_FLOW_CONTROL_RX_SHIFT))
393 
394 #define UART_NO_HARDWARE_FLOW_CONTROL UART_EFR_HW_NO_FLOW_CONTROL_VALUE
395 
396 #define UART_RTS_ENABLE UART_EFR_HW_ENABLE_RTS_VALUE
397 
398 #define UART_CTS_ENABLE UART_EFR_HW_ENALE_CTS_VALUE
399 
400 #define UART_RTS_CTS_ENABLE UART_EFR_HW_ENABLE_RTS_CTS_FLOW_CONTROL_VALUE
401 
410 #define UART_PULSE_NORMAL ( \
411  UART_MDR2_UART_PULSE_UART_PULSE_VALUE_0 << \
412  UART_MDR2_UART_PULSE_SHIFT)
413 #define UART_PULSE_SHAPING ( \
414  UART_MDR2_UART_PULSE_UART_PULSE_VALUE_1 << \
415  UART_MDR2_UART_PULSE_SHIFT)
416 
424 #define UART_TX_DMA_THRESHOLD_64 (UART_MDR3_SET_DMA_TX_THRESHOLD_64 \
425  << \
426  UART_MDR3_SET_DMA_TX_THRESHOLD_SHIFT)
427 #define UART_TX_DMA_THRESHOLD_REG (UART_MDR3_SET_DMA_TX_THRESHOLD_REG \
428  << \
429  UART_MDR3_SET_DMA_TX_THRESHOLD_SHIFT)
430 
439 #define UART_XON_ANY_ENABLE (UART_MCR_XON_EN_XON_EN_VALUE_1 << \
440  UART_MCR_XON_EN_SHIFT)
441 #define UART_XON_ANY_DISABLE (UART_MCR_XON_EN_XON_EN_VALUE_0 << \
442  UART_MCR_XON_EN_SHIFT)
443 
446 #define UART_LOOPBACK_MODE_ENABLE ( \
447  (uint32_t) UART_MCR_LOOPBACK_EN_LOOPBACK_EN_VALUE_1 << \
448  UART_MCR_LOOPBACK_EN_SHIFT)
449 #define UART_LOOPBACK_MODE_DISABLE ( \
450  (uint32_t) UART_MCR_LOOPBACK_EN_LOOPBACK_EN_VALUE_0 << \
451  UART_MCR_LOOPBACK_EN_SHIFT)
452 
455 #define UART_DCD_CONTROL (UART_MCR_CD_STS_CH_MASK)
456 #define UART_RI_CONTROL (UART_MCR_RI_STS_CH_MASK)
457 #define UART_RTS_CONTROL (UART_MCR_RTS_MASK)
458 #define UART_DTR_CONTROL (UART_MCR_DTR_MASK)
459 
462 #define UART_DCD_VALUE (UART_MSR_NCD_STS_MASK)
463 #define UART_RI_VALUE (UART_MSR_NRI_STS_MASK)
464 #define UART_DSR_VALUE (UART_MSR_NDSR_STS_MASK)
465 #define UART_CTS_VALUE (UART_MSR_NCTS_STS_MASK)
466 
469 #define UART_DCD_STS_CHANGED (UART_MSR_DCD_STS_MASK)
470 #define UART_RI_STS_CHANGED (UART_MSR_RI_STS_MASK)
471 #define UART_DSR_STS_CHANGED (UART_MSR_DSR_STS_MASK)
472 #define UART_CTS_STS_CHANGED (UART_MSR_CTS_STS_MASK)
473 
484 #define UART_RX_TRIG_LVL_GRAN_1_DISABLE ( \
485  UART_SCR_RX_TRIG_GRANU1_RX_TRIG_GRANU1_VALUE_0 << \
486  UART_SCR_RX_TRIG_GRANU1_SHIFT)
487 #define UART_RX_TRIG_LVL_GRAN_1_ENABLE ( \
488  UART_SCR_RX_TRIG_GRANU1_RX_TRIG_GRANU1_VALUE_1 << \
489  UART_SCR_RX_TRIG_GRANU1_SHIFT)
490 
491 #define UART_TX_TRIG_LVL_GRAN_1_DISABLE ( \
492  UART_SCR_TX_TRIG_GRANU1_TX_TRIG_GRANU1_VALUE_0 << \
493  UART_SCR_TX_TRIG_GRANU1_SHIFT)
494 #define UART_TX_FIFO_LVL_GRAN_1_ENABLE ( \
495  UART_SCR_TX_TRIG_GRANU1_TX_TRIG_GRANU1_VALUE_1 << \
496  UART_SCR_TX_TRIG_GRANU1_SHIFT)
497 
500 #define UART_DSRn_INT_DISABLE (UART_SCR_DSR_IT_DSR_IT_VALUE_0 << \
501  UART_SCR_DSR_IT_SHIFT)
502 #define UART_DSRn_INT_ENABLE (UART_SCR_DSR_IT_DSR_IT_VALUE_1 << \
503  UART_SCR_DSR_IT_SHIFT)
504 
508 #define UART_RX_CTS_DSR_WAKEUP_DISABLE ( \
509  UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_0 << \
510  UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT)
511 #define UART_RX_CTS_DSR_WAKEUP_ENABLE ( \
512  UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_RX_CTS_DSR_WAKE_UP_ENABLE_VALUE_1 << \
513  UART_SCR_RX_CTS_DSR_WAKE_UP_ENABLE_SHIFT)
514 
517 #define UART_THR_INT_NORMAL ( \
518  UART_SCR_TX_EMPTY_CTL_IT_TX_EMPTY_CTL_IT_VALUE_0 << \
519  UART_SCR_TX_EMPTY_CTL_IT_SHIFT)
520 #define UART_THR_INT_FIFO_TSR_EMPTY ( \
521  UART_SCR_TX_EMPTY_CTL_IT_TX_EMPTY_CTL_IT_VALUE_1 << \
522  UART_SCR_TX_EMPTY_CTL_IT_SHIFT)
523 
526 #define UART_DMA_CNTR_NO_RESET_FIFO_RESET ( \
527  UART_SSR_DMA_COUNTER_RST_DMA_COUNTER_RST_VALUE_0 << \
528  UART_SSR_DMA_COUNTER_RST_SHIFT)
529 #define UART_DMA_CNTR_RESET_FIFO_RESET ( \
530  UART_SSR_DMA_COUNTER_RST_DMA_COUNTER_RST_VALUE_1 << \
531  UART_SSR_DMA_COUNTER_RST_SHIFT)
532 
535 #define UART_RX_CTS_DSR_NO_FALL_EDGE ( \
536  UART_SSR_RX_CTS_DSR_WAKE_UP_STS_RX_CTS_DSR_WAKE_UP_STS_VALUE_0 << \
537  UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT)
538 #define UART_RX_CTS_DSR_FALL_EDGE ( \
539  UART_SSR_RX_CTS_DSR_WAKE_UP_STS_RX_CTS_DSR_WAKE_UP_STS_VALUE_1 << \
540  UART_SSR_RX_CTS_DSR_WAKE_UP_STS_SHIFT)
541 
544 #define UART_TX_FIFO_NOT_FULL ( \
545  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
546 #define UART_TX_FIFO_FULL ( \
547  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
548 
557 #define UART_SD_PIN_LOW (UART_ACREG_SD_MOD_SD_MOD_VALUE_1 \
558  << \
559  UART_ACREG_SD_MOD_SHIFT)
560 #define UART_SD_PIN_HIGH (UART_ACREG_SD_MOD_SD_MOD_VALUE_0 \
561  << \
562  UART_ACREG_SD_MOD_SHIFT)
563 
572 #define UART_IDLEMODE_FORCE_IDLE ( \
573  UART_SYSC_IDLEMODE_IDLEMODE_VALUE_0 << \
574  UART_SYSC_IDLEMODE_SHIFT)
575 #define UART_IDLEMODE_NO_IDLE ( \
576  UART_SYSC_IDLEMODE_IDLEMODE_VALUE_1 << \
577  UART_SYSC_IDLEMODE_SHIFT)
578 #define UART_IDLEMODE_SMART_IDLE ( \
579  UART_SYSC_IDLEMODE_IDLEMODE_VALUE_2 << \
580  UART_SYSC_IDLEMODE_SHIFT)
581 #define UART_IDLEMODE_SMART_IDLE_WAKEUP ( \
582  UART_SYSC_IDLEMODE_IDLEMODE_VALUE_3 << \
583  UART_SYSC_IDLEMODE_SHIFT)
584 
587 #define UART_WAKEUP_ENABLE ( \
588  UART_SYSC_ENAWAKEUP_ENAWAKEUP_VALUE_1 << \
589  UART_SYSC_ENAWAKEUP_SHIFT)
590 #define UART_WAKEUP_DISABLE ( \
591  UART_SYSC_ENAWAKEUP_ENAWAKEUP_VALUE_0 << \
592  UART_SYSC_ENAWAKEUP_SHIFT)
593 
595 #define UART_AUTO_IDLE_MODE_ENABLE ( \
596  UART_SYSC_AUTOIDLE_AUTOIDLE_VALUE_1)
597 #define UART_AUTO_IDLE_MODE_DISABLE ( \
598  UART_SYSC_AUTOIDLE_AUTOIDLE_VALUE_0)
599 
609 #define UART_WAKEUP_TX_INTERRUPT (UART_WER_EVENT_7_TX_WAKEUP_EN_MASK)
610 #define UART_WAKEUP_RLS_INTERRUPT ( \
611  UART_WER_EVENT_6_RECEIVER_LINE_STATUS_INTERRUPT_MASK)
612 #define UART_WAKEUP_RHR_INTERRUPT ( \
613  UART_WER_EVENT_5_RHR_INTERRUPT_MASK)
614 #define UART_WAKEUP_RX_ACTIVITY (UART_WER_EVENT_4_RX_ACTIVITY_MASK)
615 #define UART_WAKEUP_DCD_ACTIVITY ( \
616  UART_WER_EVENT_3_DCD_CD_ACTIVITY_MASK)
617 #define UART_WAKEUP_RI_ACTIVITY (UART_WER_EVENT_2_RI_ACTIVITY_MASK)
618 #define UART_WAKEUP_DSR_ACTIVITY (UART_WER_EVENT_1_DSR_ACTIVITY_MASK)
619 #define UART_WAKEUP_CTS_ACTIVITY (UART_WER_EVENT_0_CTS_ACTIVITY_MASK)
620 
630 #define UART_AUTOBAUD_NO_PARITY ( \
631  UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_0 << \
632  UART_UASR_PARITY_TYPE_SHIFT)
633 #define UART_AUTOBAUD_PARITY_SPACE ( \
634  UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_1 << \
635  UART_UASR_PARITY_TYPE_SHIFT)
636 #define UART_AUTOBAUD_EVEN_PARITY ( \
637  UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_2 << \
638  UART_UASR_PARITY_TYPE_SHIFT)
639 #define UART_AUTOBAUD_ODD_PARITY ( \
640  UART_UASR_PARITY_TYPE_PARITY_TYPE_U_VALUE_3 << \
641  UART_UASR_PARITY_TYPE_SHIFT)
642 
645 #define UART_AUTOBAUD_CHAR_LENGTH_7 ( \
646  UART_UASR_BIT_BY_CHAR_BIT_BY_CHAR_U_VALUE_0 << \
647  UART_UASR_BIT_BY_CHAR_SHIFT)
648 #define UART_AUTOBAUD_CHAR_LENGTH_8 ( \
649  UART_UASR_BIT_BY_CHAR_BIT_BY_CHAR_U_VALUE_1 << \
650  UART_UASR_BIT_BY_CHAR_SHIFT)
651 
654 #define UART_AUTOBAUD_NO_SPEED_IDEN (UART_UASR_SPEED_SPEED_VALUE_0)
655 #define UART_AUTOBAUD_SPEED_115200 (UART_UASR_SPEED_SPEED_VALUE_1)
656 #define UART_AUTOBAUD_SPEED_57600 (UART_UASR_SPEED_SPEED_VALUE_2)
657 #define UART_AUTOBAUD_SPEED_38400 (UART_UASR_SPEED_SPEED_VALUE_3)
658 #define UART_AUTOBAUD_SPEED_28800 (UART_UASR_SPEED_SPEED_VALUE_4)
659 #define UART_AUTOBAUD_SPEED_19200 (UART_UASR_SPEED_SPEED_VALUE_5)
660 #define UART_AUTOBAUD_SPEED_14400 (UART_UASR_SPEED_SPEED_VALUE_6)
661 #define UART_AUTOBAUD_SPEED_9600 (UART_UASR_SPEED_SPEED_VALUE_7)
662 #define UART_AUTOBAUD_SPEED_4800 (UART_UASR_SPEED_SPEED_VALUE_8)
663 #define UART_AUTOBAUD_SPEED_2400 (UART_UASR_SPEED_SPEED_VALUE_9)
664 #define UART_AUTOBAUD_SPEED_1200 (UART_UASR_SPEED_SPEED_VALUE_10)
665 
674 #define UART_TRIG_LVL_GRANULARITY_4 ((uint32_t) 0x0000U)
675 #define UART_TRIG_LVL_GRANULARITY_1 ((uint32_t) 0x0001U)
676 
680 #define UART_REG_CONFIG_MODE_A (uint32_t) (0x0080)
681 #define UART_REG_CONFIG_MODE_B (uint32_t) (0x00BF)
682 #define UART_REG_OPERATIONAL_MODE (uint32_t) (0x007F)
683 
685 #define UART_FIFO_CONFIG(txGra, rxGra, txTrig, rxTrig, txClr, rxClr, dmaEnPath, \
686  dmaMode) \
687  (((uint32_t) (txGra & 0xFU) << (uint32_t)26U) | \
688  ((uint32_t) (rxGra & 0xFU) << (uint32_t)22U) | \
689  ((uint32_t) (txTrig & 0xFFU) << (uint32_t)14U) | \
690  ((uint32_t) (rxTrig & 0xFFU) << (uint32_t)6U) | \
691  ((uint32_t) (txClr & 0x1U) << (uint32_t)5U) | \
692  ((uint32_t) (rxClr & 0x1U) << (uint32_t)4U) | \
693  ((uint32_t) (dmaEnPath & 0x1U) << (uint32_t)3U) | \
694  (uint32_t) (dmaMode & 0x7U))
695 
697 #define UART_FCR_PROGRAM(rxFIFOTrig, txFIFOTrig, dmaMode, txClr, rxClr, fifoEn) \
698  (((uint32_t) (((uint32_t) (rxFIFOTrig) & 0x3U) << 6)) | \
699  ((uint32_t) (((uint32_t) (txFIFOTrig) & 0x3U) << 4)) | \
700  (((uint32_t))(((uint32_t) (dmaMode) & 0x1U) << 3)) | \
701  (((uint32_t))(((uint32_t) (txClr) & 0x1U) << 2)) | \
702  ((uint32_t) (((uint32_t) (rxClr) & 0x1U) << 1)) | \
703  ((uint32_t) (fifoEn) & 0x1U))
704 
705 #define UART_FIFO_CONFIG_TXGRA ((uint32_t) 0xFU << 26)
706 #define UART_FIFO_CONFIG_RXGRA ((uint32_t) 0xFU << 22)
707 #define UART_FIFO_CONFIG_TXTRIG ((uint32_t) 0xFFU << 14)
708 #define UART_FIFO_CONFIG_RXTRIG ((uint32_t) 0xFFU << 6)
709 #define UART_FIFO_CONFIG_TXCLR ((uint32_t) 0x1U << 5)
710 #define UART_FIFO_CONFIG_RXCLR ((uint32_t) 0x1U << 4)
711 #define UART_FIFO_CONFIG_DMAENPATH ((uint32_t) 0x1U << 3)
712 #define UART_FIFO_CONFIG_DMAMODE ((uint32_t) 0x7U << 0)
713 
715 #define UART_MIR_OVERSAMPLING_RATE_41 ((uint32_t) 41U)
716 #define UART_MIR_OVERSAMPLING_RATE_42 ((uint32_t) 42U)
717 
718 #define UART_FCR_TX_FIFO_TRIG_8SPACES ((uint32_t) 0x0U)
719 #define UART_FCR_TX_FIFO_TRIG_16SPACES ((uint32_t) 0x1U)
720 #define UART_FCR_TX_FIFO_TRIG_32SPACES ((uint32_t) 0x2U)
721 #define UART_FCR_TX_FIFO_TRIG_56SPACES ((uint32_t) 0x3U)
722 
724 #define UART_LCR_STB_SHIFT ((uint32_t) 0x00000002U)
725 #define UART_LCR_PEN_SHIFT ((uint32_t) 0x00000003U)
726 #define UART_LCR_BC_SHIFT ((uint32_t) 0x00000006U)
727 
728 #define UART_LCR_PARITY_EN_DISABLE ((uint32_t) 0x0U)
729 
730 #define UART_MDR1_MODE_SELECT_CIR ((uint32_t) 0x6U)
731 #define UART_MDR1_MODE_SELECT_DISABLED ((uint32_t) 0x7U)
732 #define UART_MDR1_MODE_SELECT_FIR ((uint32_t) 0x5U)
733 #define UART_MDR1_MODE_SELECT_MIR ((uint32_t) 0x4U)
734 #define UART_MDR1_MODE_SELECT_SIR ((uint32_t) 0x1U)
735 #define UART_MDR1_MODE_SELECT_UART13X ((uint32_t) 0x3U)
736 #define UART_MDR1_MODE_SELECT_UART16X ((uint32_t) 0x0U)
737 #define UART_MDR1_MODE_SELECT_UART16XAUTO ((uint32_t) 0x2U)
738 
739 #define UART_FCR_RX_FIFO_TRIG_16CHAR ((uint32_t) 0x1U)
740 #define UART_FCR_RX_FIFO_TRIG_56CHAR ((uint32_t) 0x2U)
741 #define UART_FCR_RX_FIFO_TRIG_60CHAR ((uint32_t) 0x3U)
742 #define UART_FCR_RX_FIFO_TRIG_8CHAR ((uint32_t) 0x0U)
743 
744 #define UART_EFR_SW_FLOW_CONTROL_RX_SHIFT ((uint32_t) 0x0U)
745 #define UART_EFR_SW_FLOW_CONTROL_TX_SHIFT ((uint32_t) 0x2U)
746 
748 #define UART_MDR3_SET_DMA_TX_THRESHOLD_64 ((uint32_t) 0x0U)
749 #define UART_MDR3_SET_DMA_TX_THRESHOLD_REG ((uint32_t) 0x1U)
750 #define UART_MDR3_DIR_POL_0 ((uint32_t) 0U)
751 #define UART_MDR3_DIR_POL_1 ((uint32_t) 1U)
752 
755 /* ========================================================================== */
756 /* Function Declarations */
757 /* ========================================================================== */
758 
785 extern uint32_t UARTOperatingModeSelect(uint32_t baseAddr,
786  uint32_t modeFlag);
787 
817 extern uint32_t UARTDivisorValCompute(uint32_t moduleClk,
818  uint32_t baudRate,
819  uint32_t modeFlag,
820  uint32_t mirOverSampRate);
821 
833 extern uint32_t UARTDivisorLatchWrite(uint32_t baseAddr,
834  uint32_t divisorValue);
835 
845 extern void UARTDivisorLatchEnable(uint32_t baseAddr);
846 
858 extern void UARTDivisorLatchDisable(uint32_t baseAddr);
859 
884 extern uint32_t UARTRegConfigModeEnable(uint32_t baseAddr,
885  uint32_t modeFlag);
886 
903 extern void UARTRegConfModeRestore(uint32_t baseAddr,
904  uint32_t lcrRegValue);
905 
923 extern void UARTBreakCtl(uint32_t baseAddr, uint32_t breakState);
924 
963 extern void UARTLineCharacConfig(uint32_t baseAddr,
964  uint32_t wLenStbFlag,
965  uint32_t parityFlag);
966 
987 extern void UARTParityModeSet(uint32_t baseAddr, uint32_t parityFlag);
988 
1007 extern uint32_t UARTParityModeGet(uint32_t baseAddr);
1008 
1029 extern void UARTDMAEnable(uint32_t baseAddr, uint32_t dmaModeFlag);
1030 
1039 extern void UARTDMADisable(uint32_t baseAddr);
1040 
1120 extern uint32_t UARTFIFOConfig(uint32_t baseAddr,
1121  uint32_t fifoConfig);
1122 
1136 extern uint32_t UARTEnhanFuncEnable(uint32_t baseAddr);
1137 
1159 extern void UARTEnhanFuncBitValRestore(uint32_t baseAddr,
1160  uint32_t enhanFnBitVal);
1161 
1192 extern uint32_t UARTSubConfigMSRSPRModeEn(uint32_t baseAddr);
1193 
1208 extern uint32_t UARTSubConfigTCRTLRModeEn(uint32_t baseAddr);
1209 
1224 extern uint32_t UARTSubConfigXOFFModeEn(uint32_t baseAddr);
1225 
1238 extern void UARTTCRTLRBitValRestore(uint32_t baseAddr,
1239  uint32_t tcrTlrBitVal);
1240 
1270 extern void UARTIntEnable(uint32_t baseAddr, uint32_t intFlag);
1271 
1296 extern void UARTIntDisable(uint32_t baseAddr, uint32_t intFlag);
1297 
1317 extern void UARTInt2Enable(uint32_t baseAddr, uint32_t intFlag);
1318 
1336 extern void UARTInt2Disable(uint32_t baseAddr, uint32_t intFlag);
1337 
1349 extern uint32_t UARTSpaceAvail(uint32_t baseAddr);
1350 
1363 extern uint32_t UARTCharsAvail(uint32_t baseAddr);
1364 
1375 extern uint32_t UARTCharPutNonBlocking(uint32_t baseAddr,
1376  uint8_t byteWrite);
1377 
1389 extern int8_t UARTCharGetNonBlocking(uint32_t baseAddr);
1390 
1401 extern int8_t UARTCharGet(uint32_t baseAddr);
1402 
1420 extern uint8_t UARTCharGetTimeout(uint32_t baseAddr,
1421  uint32_t timeOutVal);
1422 
1434 extern void UARTCharPut(uint32_t baseAddr, uint8_t byteTx);
1435 
1454 extern void UARTFIFOCharPut(uint32_t baseAddr, uint8_t byteTx);
1455 
1475 extern int8_t UARTFIFOCharGet(uint32_t baseAddr);
1476 
1493 extern uint32_t UARTFIFOWrite(uint32_t baseAddr,
1494  const uint8_t *pBuffer,
1495  uint32_t numTxBytes);
1496 
1514 extern uint32_t UARTRxErrorGet(uint32_t baseAddr);
1515 
1539 extern uint32_t UARTIntIdentityGet(uint32_t baseAddr);
1540 
1551 extern uint32_t UARTIntPendingStatusGet(uint32_t baseAddr);
1552 
1563 extern uint32_t UARTInt2StatusGet(uint32_t baseAddr);
1564 
1575 extern uint32_t UARTFIFOEnableStatusGet(uint32_t baseAddr);
1576 
1603 extern void UARTAutoRTSAutoCTSControl(uint32_t baseAddr,
1604  uint32_t autoCtsControl,
1605  uint32_t autoRtsControl);
1606 
1628 extern void UARTSpecialCharDetectControl(uint32_t baseAddr,
1629  uint32_t controlFlag);
1630 
1654 extern void UARTSoftwareFlowCtrlOptSet(uint32_t baseAddr,
1655  uint32_t swFlowCtrl);
1656 
1676 extern void UARTHardwareFlowCtrlOptSet(uint32_t baseAddr,
1677  uint32_t hwFlowCtrl);
1678 
1695 extern void UARTPulseShapingControl(uint32_t baseAddr,
1696  uint32_t shapeControl);
1697 
1710 extern void UARTModuleReset(uint32_t baseAddr);
1711 
1728 extern void UARTIdleModeConfigure(uint32_t baseAddr, uint32_t modeFlag);
1729 
1744 extern void UARTWakeUpControl(uint32_t baseAddr, uint32_t controlFlag);
1745 
1760 extern void UARTAutoIdleModeControl(uint32_t baseAddr,
1761  uint32_t modeFlag);
1762 
1795 extern void UARTFlowCtrlTrigLvlConfig(uint32_t baseAddr,
1796  uint32_t rtsHaltFlag,
1797  uint32_t rtsStartFlag);
1798 
1811 extern void UARTXON1XOFF1ValProgram(uint32_t baseAddr,
1812  uint8_t xon1Value,
1813  uint8_t xoff1Value);
1814 
1828 extern void UARTXON2XOFF2ValProgram(uint32_t baseAddr,
1829  uint8_t xon2Value,
1830  uint8_t xoff2Value);
1831 
1850 extern void UARTXONAnyFeatureControl(uint32_t baseAddr,
1851  uint32_t controlFlag);
1852 
1867 extern void UARTLoopbackModeControl(uint32_t baseAddr,
1868  uint32_t controlFlag);
1869 
1889 extern void UARTModemControlSet(uint32_t baseAddr, uint32_t modeFlag);
1890 
1911 extern void UARTModemControlClear(uint32_t baseAddr, uint32_t modeFlag);
1912 
1930 extern uint32_t UARTModemStatusGet(uint32_t baseAddr);
1931 
1950 extern uint32_t UARTModemStatusChangeCheck(uint32_t baseAddr);
1951 
1966 extern void UARTResumeOperation(uint32_t baseAddr);
1967 
1997 extern void UARTWakeUpEventsEnable(uint32_t baseAddr,
1998  uint32_t wakeUpFlag);
1999 
2029 extern void UARTWakeUpEventsDisable(uint32_t baseAddr,
2030  uint32_t wakeUpFlag);
2031 
2056 extern void UARTFIFOTrigLvlGranControl(uint32_t baseAddr,
2057  uint32_t rxFIFOGranCtrl,
2058  uint32_t txFIFOGranCtrl);
2059 
2074 extern void UARTDSRInterruptControl(uint32_t baseAddr,
2075  uint32_t controlFlag);
2076 
2096 extern void UARTTxEmptyIntControl(uint32_t baseAddr,
2097  uint32_t controlFlag);
2098 
2117 extern void UARTRXCTSDSRWakeUpConfigure(uint32_t baseAddr,
2118  uint32_t wakeUpFlag);
2119 
2133 extern uint32_t UARTRXCTSDSRTransitionStatusGet(uint32_t baseAddr);
2134 
2150 extern void UARTDMACounterResetControl(uint32_t baseAddr,
2151  uint32_t controlFlag);
2152 
2163 extern uint32_t UARTTxFIFOFullStatusGet(uint32_t baseAddr);
2164 
2173 extern uint32_t UARTTxFIFOLevelGet(uint32_t baseAddr);
2174 
2183 extern uint32_t UARTRxFIFOLevelGet(uint32_t baseAddr);
2184 
2205 extern uint32_t UARTAutobaudParityGet(uint32_t baseAddr);
2206 
2221 extern uint32_t UARTAutobaudWordLenGet(uint32_t baseAddr);
2222 
2246 extern uint32_t UARTAutobaudSpeedGet(uint32_t baseAddr);
2247 
2258 extern void UARTScratchPadRegWrite(uint32_t baseAddr,
2259  uint32_t scratchValue);
2260 
2269 extern uint32_t UARTScratchPadRegRead(uint32_t baseAddr);
2270 
2281 extern uint32_t UARTModuleVersionNumberGet(uint32_t baseAddr);
2282 
2319 extern void UARTFIFORegisterWrite(uint32_t baseAddr, uint32_t fcrValue);
2320 
2339 extern void UARTTxDMAThresholdControl(uint32_t baseAddr, uint32_t thrsCtrlFlag);
2340 
2355 extern void UARTTxDMAThresholdValConfig(uint32_t baseAddr, uint32_t thrsValue);
2356 
2388 extern void UARTFIFOLevelSet(uint32_t baseAddr, uint32_t rxLevel);
2389 
2400 extern uint32_t UARTModemControlGet(uint32_t baseAddr);
2401 
2412 extern void UARTFIFOCtrlRegWrite(uint32_t baseAddr, uint32_t fcrValue);
2413 
2421 extern void UARTModemControlReset(uint32_t baseAddr);
2422 
2432 extern uint32_t UARTReadStatus(uint32_t baseAddr);
2433 
2446 extern uint32_t UARTIsTransmitterEmpty(uint32_t baseAddr);
2447 
2460 extern uint32_t UARTCharGetNonBlocking2(uint32_t baseAddr, uint8_t *pChar);
2461 
2484 extern uint32_t UARTCharGetTimeout2(uint32_t baseAddr,
2485  uint32_t timeOutVal,
2486  uint8_t *pChar);
2487 
2499 extern void UARTDirPolSet(uint32_t baseAddr, uint32_t dirPol);
2500 
2510 extern void UARTDirEnControl(uint32_t baseAddr, uint32_t dirEnFlag);
2511 
2525 extern void UARTSetTimeOutValue(uint32_t baseAddr, uint16_t timeoutIntrVal, uint32_t timeoutBehavior);
2526 
2527 #ifdef __cplusplus
2528 }
2529 #endif
2530 #endif
2531 
2532 /********************************* End of File********************************/
2533 
UARTIntDisable
void UARTIntDisable(uint32_t baseAddr, uint32_t intFlag)
This API disables the specified interrupts in the UART mode of operation.
UARTFIFOCharPut
void UARTFIFOCharPut(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
UARTTxFIFOLevelGet
uint32_t UARTTxFIFOLevelGet(uint32_t baseAddr)
This API determines the current level of the Transmitter FIFO.
UARTSubConfigTCRTLRModeEn
uint32_t UARTSubConfigTCRTLRModeEn(uint32_t baseAddr)
This API enables the TCR_TLR Sub_Configuration Mode of operation.
UARTCharGetTimeout2
uint32_t UARTCharGetTimeout2(uint32_t baseAddr, uint32_t timeOutVal, uint8_t *pChar)
This API waits for the arrival of atleast one byte into the Receiver FIFO or until a specified timeou...
UARTIntIdentityGet
uint32_t UARTIntIdentityGet(uint32_t baseAddr)
This API determines the UART Interrupt Status.
UARTCharGetTimeout
uint8_t UARTCharGetTimeout(uint32_t baseAddr, uint32_t timeOutVal)
This API waits for the arrival of atleast one byte into the Receiver FIFO or until a specified timeou...
UARTModemControlSet
void UARTModemControlSet(uint32_t baseAddr, uint32_t modeFlag)
This API switches the specified Modem Control Signals to active state. The Modem Control signals in c...
UARTWakeUpEventsEnable
void UARTWakeUpEventsEnable(uint32_t baseAddr, uint32_t wakeUpFlag)
This API enables the Wake-Up capability for the specified events. On enabling Wake-Up capability for ...
UARTCharPutNonBlocking
uint32_t UARTCharPutNonBlocking(uint32_t baseAddr, uint8_t byteWrite)
This API attempts to write a byte into Transmitter Holding Register (THR). It checks only once if the...
UARTParityModeGet
uint32_t UARTParityModeGet(uint32_t baseAddr)
This API reads the Parity configuration being set in the UART.
UARTXONAnyFeatureControl
void UARTXONAnyFeatureControl(uint32_t baseAddr, uint32_t controlFlag)
This API controls(enables/disables) the XON-any feature in Modem Control Register(MCR).
UARTHardwareFlowCtrlOptSet
void UARTHardwareFlowCtrlOptSet(uint32_t baseAddr, uint32_t hwFlowCtrl)
This API configures the options for hardware Flow Control.
UARTDivisorValCompute
uint32_t UARTDivisorValCompute(uint32_t moduleClk, uint32_t baudRate, uint32_t modeFlag, uint32_t mirOverSampRate)
This API computes the divisor value for the specified operating mode. Not part of this API,...
UARTDMAEnable
void UARTDMAEnable(uint32_t baseAddr, uint32_t dmaModeFlag)
This API enables the DMA mode of operation for the UART instance.
UARTModemControlClear
void UARTModemControlClear(uint32_t baseAddr, uint32_t modeFlag)
This API switches the specified Modem Control signals to inactive state. The Modem Control signals in...
UARTLoopbackModeControl
void UARTLoopbackModeControl(uint32_t baseAddr, uint32_t controlFlag)
This API controls(enables/disables) the Loopback mode of operation for the UART instance.
UARTFIFOCharGet
int8_t UARTFIFOCharGet(uint32_t baseAddr)
This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding R...
UARTIntEnable
void UARTIntEnable(uint32_t baseAddr, uint32_t intFlag)
This API enables the specified interrupts in the UART mode of operation.
UARTAutoIdleModeControl
void UARTAutoIdleModeControl(uint32_t baseAddr, uint32_t modeFlag)
This API is used to control(enable/disable) the Auto-Idle mode of operation of the UART.
UARTFlowCtrlTrigLvlConfig
void UARTFlowCtrlTrigLvlConfig(uint32_t baseAddr, uint32_t rtsHaltFlag, uint32_t rtsStartFlag)
This API configures the Receiver FIFO threshold level to start/stop transmission during Hardware Flow...
UARTModuleVersionNumberGet
uint32_t UARTModuleVersionNumberGet(uint32_t baseAddr)
This API reads the Revision Number of the module from the Module Version Register(MVR).
UARTIsTransmitterEmpty
uint32_t UARTIsTransmitterEmpty(uint32_t baseAddr)
This API returns the transmitter empty status i.e. if Transmitter FIFO (THR register in non-FIFO mode...
UARTTxFIFOFullStatusGet
uint32_t UARTTxFIFOFullStatusGet(uint32_t baseAddr)
This API determines whether the Transmitter FIFO is full or not.
UARTModemStatusChangeCheck
uint32_t UARTModemStatusChangeCheck(uint32_t baseAddr)
This API determines if the values on Modem Signal Lines have changed since the last read of Modem Sta...
UARTBreakCtl
void UARTBreakCtl(uint32_t baseAddr, uint32_t breakState)
This API is used to introduce or to remove a Break condition.
UARTCharPut
void UARTCharPut(uint32_t baseAddr, uint8_t byteTx)
This API waits indefinitely until the Transmitter FIFO (THR register in non-FIFO mode) and Transmitte...
UARTEnhanFuncBitValRestore
void UARTEnhanFuncBitValRestore(uint32_t baseAddr, uint32_t enhanFnBitVal)
This API restores the ENHANCEDEN bit value of EFR register(EFR[4]) to the corresponding bit value in ...
UARTAutobaudWordLenGet
uint32_t UARTAutobaudWordLenGet(uint32_t baseAddr)
This API determines the word length per frame(character length) being configured by the system in UAR...
UARTModemStatusGet
uint32_t UARTModemStatusGet(uint32_t baseAddr)
This API reads the values on Modem Signal Lines. The Modem Signals in context are: 1> Data Carrier De...
UARTXON2XOFF2ValProgram
void UARTXON2XOFF2ValProgram(uint32_t baseAddr, uint8_t xon2Value, uint8_t xoff2Value)
This API programs the XON2/ADDR2 and XOFF2 registers.
UARTResumeOperation
void UARTResumeOperation(uint32_t baseAddr)
This API reads the RESUME register which clears the internal flags.
UARTDivisorLatchDisable
void UARTDivisorLatchDisable(uint32_t baseAddr)
This API disables write access to Divisor Latch registers DLL and DLH.
UARTInt2StatusGet
uint32_t UARTInt2StatusGet(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
UARTSoftwareFlowCtrlOptSet
void UARTSoftwareFlowCtrlOptSet(uint32_t baseAddr, uint32_t swFlowCtrl)
This API configures the options for Software Flow Control.
UARTModuleReset
void UARTModuleReset(uint32_t baseAddr)
This API performs a module reset of the UART instance. It also waits until the reset process is compl...
UARTSubConfigXOFFModeEn
uint32_t UARTSubConfigXOFFModeEn(uint32_t baseAddr)
This API enables the XOFF Sub-Configuration Mode of operation.
UARTRxFIFOLevelGet
uint32_t UARTRxFIFOLevelGet(uint32_t baseAddr)
This API determines the current level of the Receiver FIFO.
UARTFIFOTrigLvlGranControl
void UARTFIFOTrigLvlGranControl(uint32_t baseAddr, uint32_t rxFIFOGranCtrl, uint32_t txFIFOGranCtrl)
This API controls the feature of setting the Trigger Level granularity as 1 for Transmitter and Recei...
UARTFIFOCtrlRegWrite
void UARTFIFOCtrlRegWrite(uint32_t baseAddr, uint32_t fcrValue)
This API is used to write a specified value to the FIFO Control Register(FCR) without disabling the d...
UARTFIFORegisterWrite
void UARTFIFORegisterWrite(uint32_t baseAddr, uint32_t fcrValue)
This API is used to write a specified value to the FIFO Control Register(FCR).
UARTAutobaudSpeedGet
uint32_t UARTAutobaudSpeedGet(uint32_t baseAddr)
This API determines the baud rate being configured by the system in UART Autobauding mode.
UARTTxEmptyIntControl
void UARTTxEmptyIntControl(uint32_t baseAddr, uint32_t controlFlag)
This API is used to choose a condition under which a Transmit Holding Register(THR) Interrupt should ...
UARTAutoRTSAutoCTSControl
void UARTAutoRTSAutoCTSControl(uint32_t baseAddr, uint32_t autoCtsControl, uint32_t autoRtsControl)
This API controls the use of Auto-RTS and Auto-CTS features which are used in Hardware Flow Control M...
UARTModemControlGet
uint32_t UARTModemControlGet(uint32_t baseAddr)
This function gets the status of the RTS and AFE bits in the MCR register.
UARTSetTimeOutValue
void UARTSetTimeOutValue(uint32_t baseAddr, uint16_t timeoutIntrVal, uint32_t timeoutBehavior)
This API is used to set the timeout value and the TIMEOUT_BEHAVE.
UARTRegConfigModeEnable
uint32_t UARTRegConfigModeEnable(uint32_t baseAddr, uint32_t modeFlag)
This API configures the specified Register Configuration mode for the UART.
UARTFIFOWrite
uint32_t UARTFIFOWrite(uint32_t baseAddr, const uint8_t *pBuffer, uint32_t numTxBytes)
This API copies the requested amount of data from the pointed data block to the UART Transmit FIFO.
UARTSpecialCharDetectControl
void UARTSpecialCharDetectControl(uint32_t baseAddr, uint32_t controlFlag)
This API controls the feature of detecting a Special Character arriving in the receiver.
UARTDirEnControl
void UARTDirEnControl(uint32_t baseAddr, uint32_t dirEnFlag)
This API is used to control the RS-485 External Transceiver Direction.
UARTInt2Disable
void UARTInt2Disable(uint32_t baseAddr, uint32_t intFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
UARTModemControlReset
void UARTModemControlReset(uint32_t baseAddr)
This API resets the Modem control register.
UARTWakeUpControl
void UARTWakeUpControl(uint32_t baseAddr, uint32_t controlFlag)
This API is used to control(enable/disable) the Wake-Up feature of the UART.
UARTOperatingModeSelect
uint32_t UARTOperatingModeSelect(uint32_t baseAddr, uint32_t modeFlag)
This API configures the operating mode for the UART instance. The different operating modes are:
UARTRegConfModeRestore
void UARTRegConfModeRestore(uint32_t baseAddr, uint32_t lcrRegValue)
This API is used to restore the UART to the specified Register Configuration Mode.
UARTWakeUpEventsDisable
void UARTWakeUpEventsDisable(uint32_t baseAddr, uint32_t wakeUpFlag)
This API disables the Wake-Up capability for the specified events. On disabling Wake-Up capability fo...
UARTScratchPadRegRead
uint32_t UARTScratchPadRegRead(uint32_t baseAddr)
This API reads the value in Scratchpad Register.
UARTPulseShapingControl
void UARTPulseShapingControl(uint32_t baseAddr, uint32_t shapeControl)
Used only in UART mode, this API is used to control the pulse shaping feature. Pulse shaping feature ...
UARTDivisorLatchEnable
void UARTDivisorLatchEnable(uint32_t baseAddr)
This API enables write access to Divisor Latch registers DLL and DLH.
UARTAutobaudParityGet
uint32_t UARTAutobaudParityGet(uint32_t baseAddr)
This API determines the Parity mode being configured by the system in the UART Autobauding mode.
UARTDivisorLatchWrite
uint32_t UARTDivisorLatchWrite(uint32_t baseAddr, uint32_t divisorValue)
This API is used to write the specified divisor value to Divisor Latch registers DLL and DLH.
UARTDMACounterResetControl
void UARTDMACounterResetControl(uint32_t baseAddr, uint32_t controlFlag)
This API controls the DMA Counter Reset options.
UARTIdleModeConfigure
void UARTIdleModeConfigure(uint32_t baseAddr, uint32_t modeFlag)
This API can be used to control the Power Management request/acknowledgement process.
UARTCharsAvail
uint32_t UARTCharsAvail(uint32_t baseAddr)
This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.
UARTTxDMAThresholdValConfig
void UARTTxDMAThresholdValConfig(uint32_t baseAddr, uint32_t thrsValue)
This function programs the TX_DMA_THRESHOLD register which holds Transmit DMA Threshold value to be u...
UARTRxErrorGet
uint32_t UARTRxErrorGet(uint32_t baseAddr)
This API reads the receiver data error status.
UARTDirPolSet
void UARTDirPolSet(uint32_t baseAddr, uint32_t dirPol)
This API is used to set the RS-485 External Transceiver Direction Polarity.
UARTParityModeSet
void UARTParityModeSet(uint32_t baseAddr, uint32_t parityFlag)
This API configures the Parity feature for the UART.
UARTFIFOEnableStatusGet
uint32_t UARTFIFOEnableStatusGet(uint32_t baseAddr)
This API determines whether FIFO mode of operation is enabled for the UART instance or not.
UARTReadStatus
uint32_t UARTReadStatus(uint32_t baseAddr)
This API reads the line status register value.
UARTTxDMAThresholdControl
void UARTTxDMAThresholdControl(uint32_t baseAddr, uint32_t thrsCtrlFlag)
This function controls the method of setting the Transmit DMA Threshold Value. The Transmit DMA Thres...
UARTEnhanFuncEnable
uint32_t UARTEnhanFuncEnable(uint32_t baseAddr)
This API sets a certain bit in Enhanced Feature Register(EFR) which shall avail the UART to use some ...
UARTCharGetNonBlocking
int8_t UARTCharGetNonBlocking(uint32_t baseAddr)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
UARTInt2Enable
void UARTInt2Enable(uint32_t baseAddr, uint32_t intFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
UARTDSRInterruptControl
void UARTDSRInterruptControl(uint32_t baseAddr, uint32_t controlFlag)
This API controls the interrupt enable and disable feature for Data Set Ready(DSRn) interrupt.
UARTIntPendingStatusGet
uint32_t UARTIntPendingStatusGet(uint32_t baseAddr)
This API determines whether any UART interrupt condition is still alive and is pending to be serviced...
UARTFIFOConfig
uint32_t UARTFIFOConfig(uint32_t baseAddr, uint32_t fifoConfig)
This API configures the FIFO settings for the UART instance. Specifically, this does the following co...
UARTSubConfigMSRSPRModeEn
uint32_t UARTSubConfigMSRSPRModeEn(uint32_t baseAddr)
This API enables the MSR_SPR Sub-Configuration Mode of operation.
UARTRXCTSDSRWakeUpConfigure
void UARTRXCTSDSRWakeUpConfigure(uint32_t baseAddr, uint32_t wakeUpFlag)
This API controls (enables/disables) a feature where a falling edge on the RX, CTSn or DSRs could sen...
UARTDMADisable
void UARTDMADisable(uint32_t baseAddr)
This API disables the DMA mode of operation.
UARTLineCharacConfig
void UARTLineCharacConfig(uint32_t baseAddr, uint32_t wLenStbFlag, uint32_t parityFlag)
This API configures the Line Characteristics for the UART instance. The Line Characteristics include:
UARTXON1XOFF1ValProgram
void UARTXON1XOFF1ValProgram(uint32_t baseAddr, uint8_t xon1Value, uint8_t xoff1Value)
This API programs the XON1/ADDR1 and XOFF1 registers.
UARTFIFOLevelSet
void UARTFIFOLevelSet(uint32_t baseAddr, uint32_t rxLevel)
This function sets the receiver FIFO trigger level. .
UARTSpaceAvail
uint32_t UARTSpaceAvail(uint32_t baseAddr)
This API checks whether the TX FIFO (or THR in non-FIFO mode) is empty or not.
UARTRXCTSDSRTransitionStatusGet
uint32_t UARTRXCTSDSRTransitionStatusGet(uint32_t baseAddr)
This API determines whether a falling edge occured on RX, CTSn or DSRn lines.
UARTCharGetNonBlocking2
uint32_t UARTCharGetNonBlocking2(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
UARTTCRTLRBitValRestore
void UARTTCRTLRBitValRestore(uint32_t baseAddr, uint32_t tcrTlrBitVal)
This API restores the TCRTLR bit(MCR[6]) value in Modem Control Register(MCR) to the corresponding bi...
UARTCharGet
int8_t UARTCharGet(uint32_t baseAddr)
This API waits indefinitely for the arrival of a byte in the receiver FIFO. Once a byte has arrived,...
UARTScratchPadRegWrite
void UARTScratchPadRegWrite(uint32_t baseAddr, uint32_t scratchValue)
This API programs the Scratchpad Register with the specified value.