56 #include <sdl_types.h> 57 #include <tistdtypes.h> 60 #include <src/sdl/hw_types.h> 62 #if defined (SOC_J721E) 64 #include <include/soc/j721e/sdlr_soc_baseaddress.h> 67 #if defined (SOC_J7200) 68 #include <src/sdl/dcc/soc/j7200/sdl_soc_dcc.h> 69 #include <include/soc/j7200/sdlr_soc_baseaddress.h> 72 #if defined (SOC_J721S2) 73 #include <src/sdl/dcc/soc/j721s2/sdl_soc_dcc.h> 74 #include <include/soc/j721s2/sdlr_soc_baseaddress.h> 77 #if defined (SOC_J784S4) 78 #include <src/sdl/dcc/soc/j784s4/sdl_soc_dcc.h> 79 #include <include/soc/j784s4/sdlr_soc_baseaddress.h> 119 #define DCC_SRC0_COUNT_MAX (0xFFFFFU) 123 #define DCC_SRC0_VALID_MAX (0x0FFFFU) 127 #define DCC_SRC1_COUNT_MAX (0xFFFFFU) 129 #define MIN_CLK0_VLD_SEED (4u) 154 #define SDL_DCC_MODE_SINGLE_SHOT_1 (DCC_DCCGCTRL_SINGLESHOT_MODE1) 156 #define SDL_DCC_MODE_SINGLE_SHOT_2 (DCC_DCCGCTRL_SINGLESHOT_MODE2) 158 #define SDL_DCC_MODE_CONTINUOUS (DCC_DCCGCTRL_SINGLESHOT_DISABLE) 172 #define SDL_DCC_CLK0_SRC_CLOCK0_0 (DCC_DCCCLKSRC0_CLKSRC0_0) 174 #define SDL_DCC_CLK0_SRC_CLOCK0_1 (DCC_DCCCLKSRC0_CLKSRC0_1) 176 #define SDL_DCC_CLK0_SRC_CLOCK0_2 (DCC_DCCCLKSRC0_CLKSRC0_2) 189 #define SDL_DCC_CLK1_SRC_CLOCK1 (DCC_DCCCLKSRC1_CLKSRC_0) 191 #define SDL_DCC_CLK1_SRC_CLOCKSRC0 (DCC_DCCCLKSRC1_CLKSRC_1) 193 #define SDL_DCC_CLK1_SRC_CLOCKSRC1 (DCC_DCCCLKSRC1_CLKSRC_2) 195 #define SDL_DCC_CLK1_SRC_CLOCKSRC2 (DCC_DCCCLKSRC1_CLKSRC_3) 197 #define SDL_DCC_CLK1_SRC_CLOCKSRC3 (DCC_DCCCLKSRC1_CLKSRC_4) 199 #define SDL_DCC_CLK1_SRC_CLOCKSRC4 (DCC_DCCCLKSRC1_CLKSRC_5) 201 #define SDL_DCC_CLK1_SRC_CLOCKSRC5 (DCC_DCCCLKSRC1_CLKSRC_6) 203 #define SDL_DCC_CLK1_SRC_CLOCKSRC6 (DCC_DCCCLKSRC1_CLKSRC_7) 205 #define SDL_DCC_CLK1_SRC_CLOCKSRC7 (DCC_DCCCLKSRC1_CLKSRC_8) 207 #define SDL_DCC_CLK1_SRC_FICLK (DCC_DCCCLKSRC1_CLKSRC_OTHER) 221 #define SDL_DCC_INTERRUPT_ERR (0x0U) 223 #define SDL_DCC_INTERRUPT_DONE (0x1U) 242 typedef struct SDL_DCC_config_st
265 typedef struct SDL_DCC_status_st
282 typedef struct SDL_DCC_staticRegs_st
390 #define DCC_DCCGCTRL (0x0U) 391 #define DCC_DCCREV (0x4U) 392 #define DCC_DCCCNTSEED0 (0x8U) 393 #define DCC_DCCVALIDSEED0 (0xcU) 394 #define DCC_DCCCNTSEED1 (0x10U) 395 #define DCC_DCCSTAT (0x14U) 396 #define DCC_DCCCNT0 (0x18U) 397 #define DCC_DCCVALID0 (0x1cU) 398 #define DCC_DCCCNT1 (0x20U) 399 #define DCC_DCCCLKSRC1 (0x24U) 400 #define DCC_DCCCLKSRC0 (0x28U) 406 #define DCC_DCCGCTRL_DCCENA_SHIFT (0U) 407 #define DCC_DCCGCTRL_DCCENA_MASK (0x0000000fU) 408 #define DCC_DCCGCTRL_DCCENA_ENABLE (0xFU) 409 #define DCC_DCCGCTRL_DCCENA_DISABLE (0x5U) 411 #define DCC_DCCGCTRL_ERRENA_SHIFT (4U) 412 #define DCC_DCCGCTRL_ERRENA_MASK (0x000000f0U) 413 #define DCC_DCCGCTRL_ERRENA_ENABLE (0xFU) 414 #define DCC_DCCGCTRL_ERRENA_DISABLE (0x5U) 416 #define DCC_DCCGCTRL_SINGLESHOT_SHIFT (8U) 417 #define DCC_DCCGCTRL_SINGLESHOT_MASK (0x00000f00U) 418 #define DCC_DCCGCTRL_SINGLESHOT_MODE1 (0xAU) 419 #define DCC_DCCGCTRL_SINGLESHOT_MODE2 (0xBU) 420 #define DCC_DCCGCTRL_SINGLESHOT_DISABLE (0x0U) 422 #define DCC_DCCGCTRL_DONEENA_SHIFT (12U) 423 #define DCC_DCCGCTRL_DONEENA_MASK (0x0000f000U) 424 #define DCC_DCCGCTRL_DONEENA_ENABLE (0xFU) 425 #define DCC_DCCGCTRL_DONEENA_DISABLE (0x5U) 427 #define DCC_DCCGCTRL_RES_SHIFT (16U) 428 #define DCC_DCCGCTRL_RES_MASK (0xffff0000U) 430 #define DCC_DCCREV_MINOR_SHIFT (0U) 431 #define DCC_DCCREV_MINOR_MASK (0x0000003fU) 433 #define DCC_DCCREV_CUSTOM_SHIFT (6U) 434 #define DCC_DCCREV_CUSTOM_MASK (0x000000c0U) 436 #define DCC_DCCREV_MAJOR_SHIFT (8U) 437 #define DCC_DCCREV_MAJOR_MASK (0x00000700U) 439 #define DCC_DCCREV_RTL_SHIFT (11U) 440 #define DCC_DCCREV_RTL_MASK (0x0000f800U) 442 #define DCC_DCCREV_FUNC_SHIFT (16U) 443 #define DCC_DCCREV_FUNC_MASK (0x0fff0000U) 445 #define DCC_DCCREV_RES_SHIFT (28U) 446 #define DCC_DCCREV_RES_MASK (0x30000000U) 448 #define DCC_DCCREV_SCHEME_SHIFT (30U) 449 #define DCC_DCCREV_SCHEME_MASK (0xc0000000U) 451 #define DCC_DCCCNTSEED0_COUNTSEED0_SHIFT (0U) 452 #define DCC_DCCCNTSEED0_COUNTSEED0_MASK (0x000fffffU) 454 #define DCC_DCCCNTSEED0_RES_SHIFT (20U) 455 #define DCC_DCCCNTSEED0_RES_MASK (0xfff00000U) 457 #define DCC_DCCVALIDSEED0_VALIDSEED0_SHIFT (0U) 458 #define DCC_DCCVALIDSEED0_VALIDSEED0_MASK (0x0000ffffU) 460 #define DCC_DCCVALIDSEED0_RES_SHIFT (16U) 461 #define DCC_DCCVALIDSEED0_RES_MASK (0xffff0000U) 463 #define DCC_DCCCNTSEED1_COUNTSEED1_SHIFT (0U) 464 #define DCC_DCCCNTSEED1_COUNTSEED1_MASK (0x000fffffU) 466 #define DCC_DCCCNTSEED1_RES_SHIFT (20U) 467 #define DCC_DCCCNTSEED1_RES_MASK (0xfff00000U) 469 #define DCC_DCCSTAT_ERRFLG_SHIFT (0U) 470 #define DCC_DCCSTAT_ERRFLG_MASK (0x00000001U) 472 #define DCC_DCCSTAT_DONEFLG_SHIFT (1U) 473 #define DCC_DCCSTAT_DONEFLG_MASK (0x00000002U) 475 #define DCC_DCCSTAT_RES_SHIFT (2U) 476 #define DCC_DCCSTAT_RES_MASK (0xfffffffcU) 478 #define DCC_DCCCNT0_COUNT0_SHIFT (0U) 479 #define DCC_DCCCNT0_COUNT0_MASK (0x000fffffU) 481 #define DCC_DCCCNT0_RES_SHIFT (20U) 482 #define DCC_DCCCNT0_RES_MASK (0xfff00000U) 484 #define DCC_DCCVALID0_VALID0_SHIFT (0U) 485 #define DCC_DCCVALID0_VALID0_MASK (0x0000ffffU) 487 #define DCC_DCCVALID0_RES_SHIFT (16U) 488 #define DCC_DCCVALID0_RES_MASK (0xffff0000U) 490 #define DCC_DCCCNT1_COUNT1_SHIFT (0U) 491 #define DCC_DCCCNT1_COUNT1_MASK (0x000fffffU) 493 #define DCC_DCCCNT1_RES_SHIFT (20U) 494 #define DCC_DCCCNT1_RES_MASK (0xfff00000U) 496 #define DCC_DCCCLKSRC1_CLKSRC_SHIFT (0U) 497 #define DCC_DCCCLKSRC1_CLKSRC_MASK (0x0000000fU) 498 #define DCC_DCCCLKSRC1_CLKSRC_0 (0x0U) 499 #define DCC_DCCCLKSRC1_CLKSRC_1 (0x1U) 500 #define DCC_DCCCLKSRC1_CLKSRC_2 (0x2U) 501 #define DCC_DCCCLKSRC1_CLKSRC_3 (0x3U) 502 #define DCC_DCCCLKSRC1_CLKSRC_4 (0x4U) 503 #define DCC_DCCCLKSRC1_CLKSRC_5 (0x5U) 504 #define DCC_DCCCLKSRC1_CLKSRC_6 (0x6U) 505 #define DCC_DCCCLKSRC1_CLKSRC_7 (0x7U) 506 #define DCC_DCCCLKSRC1_CLKSRC_8 (0x8U) 507 #define DCC_DCCCLKSRC1_CLKSRC_OTHER (0xFU) 509 #define DCC_DCCCLKSRC1_RES1_SHIFT (4U) 510 #define DCC_DCCCLKSRC1_RES1_MASK (0x00000ff0U) 512 #define DCC_DCCCLKSRC1_KEY_SHIFT (12U) 513 #define DCC_DCCCLKSRC1_KEY_MASK (0x0000f000U) 514 #define DCC_DCCCLKSRC1_KEY_ENABLE (0xAU) 515 #define DCC_DCCCLKSRC1_KEY_DISABLE (0x0U) 517 #define DCC_DCCCLKSRC1_RES0_SHIFT (16U) 518 #define DCC_DCCCLKSRC1_RES0_MASK (0xffff0000U) 520 #define DCC_DCCCLKSRC0_CLKSRC0_SHIFT (0U) 521 #define DCC_DCCCLKSRC0_CLKSRC0_MASK (0x0000000fU) 522 #define DCC_DCCCLKSRC0_CLKSRC0_0 (0x0U) 523 #define DCC_DCCCLKSRC0_CLKSRC0_1 (0x1U) 524 #define DCC_DCCCLKSRC0_CLKSRC0_2 (0x2U) 526 #define DCC_DCCCLKSRC0_RES1_SHIFT (4U) 527 #define DCC_DCCCLKSRC0_RES1_MASK (0x00000ff0U) 529 #define DCC_DCCCLKSRC0_KEY_SHIFT (12U) 530 #define DCC_DCCCLKSRC0_KEY_MASK (0x0000f000U) 531 #define DCC_DCCCLKSRC0_KEY_ENABLE (0xAU) 532 #define DCC_DCCCLKSRC0_KEY_DISABLE (0x0U) 534 #define DCC_DCCCLKSRC0_RES0_SHIFT (16U) 535 #define DCC_DCCCLKSRC0_RES0_MASK (0xffff0000U) uint32_t DCC_CLKSRC1
Definition: sdl_dcc.h:292
uint32_t clk0Cnt
Definition: sdl_dcc.h:273
SDL_DCC_Inst
Definition: sdl_soc_dcc.h:72
uint32_t DCC_CNTSEED0
Definition: sdl_dcc.h:286
uint32_t SDL_DCC_mode
Enum to select the DCC Operation Mode.
Definition: sdl_dcc.h:152
Definition: sdl_dcc.h:265
uint32_t SDL_DCC_clkSrc1
Enum to select the COUNT1 clock source.
Definition: sdl_dcc.h:188
uint32_t clk0Valid
Definition: sdl_dcc.h:275
int32_t SDL_DCC_getStaticRegs(SDL_DCC_Inst instance, SDL_DCC_staticRegs *pStaticRegs)
This API is used to get the value of static registers for DCC module.
uint32_t DCC_CNTSEED1
Definition: sdl_dcc.h:290
int32_t SDL_DCC_verifyConfig(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to verify the configuration for DCC module.
Definition: sdl_dcc.h:282
uint32_t DCC_CLKSRC0
Definition: sdl_dcc.h:294
SDL_DCC_config * config
Definition: sdl_dcc.h:271
int32_t SDL_DCC_clearIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to clear the interrupts.
SDL_DCC_mode mode
Definition: sdl_dcc.h:244
uint32_t SDL_DCC_intrType
Enum for DCC interrupts.
Definition: sdl_dcc.h:219
bool errIntr
Definition: sdl_dcc.h:269
SDL_DCC_clkSrc0 clk0Src
Definition: sdl_dcc.h:248
int32_t SDL_DCC_disable(SDL_DCC_Inst instance)
This API is used to disable the DCC module.
uint32_t clk1Src
Definition: sdl_dcc.h:252
int32_t SDL_DCC_getStatus(SDL_DCC_Inst instance, SDL_DCC_status *pStatus)
This API is used to get the stauts of DCC module.
uint32_t clk1Cnt
Definition: sdl_dcc.h:277
Structure containing parameters for DCC module configuration.
Definition: sdl_dcc.h:242
uint32_t DCC_VALIDSEED0
Definition: sdl_dcc.h:288
uint32_t DCC_REV
Definition: sdl_dcc.h:284
uint32_t clk0Seed
Definition: sdl_dcc.h:256
uint32_t clk0ValidSeed
Definition: sdl_dcc.h:258
uint32_t clk1Seed
Definition: sdl_dcc.h:260
int32_t SDL_DCC_enableIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to Enable the interrupts.
bool doneIntr
Definition: sdl_dcc.h:267
int32_t SDL_DCC_configure(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to configure DCC module.
uint32_t SDL_DCC_clkSrc0
Enum to select the COUNT0 clock source.
Definition: sdl_dcc.h:170
int32_t SDL_DCC_enable(SDL_DCC_Inst instance)
This API is used to enable the DCC module.