SDL API Guide for J721E
sdl_ecc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2018-2023
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
47 #ifndef INCLUDE_SDL_ECC_H_
48 #define INCLUDE_SDL_ECC_H_
49 
50 #include <stdint.h>
51 #include <stdbool.h>
52 
53 #include "sdl_common.h"
54 #include <src/ip/sdl_ip_ecc.h>
55 #include <src/ip/sdl_esm.h>
56 
57 #if defined (SOC_J721E)
58 #define SDL_MCU_R5F0_SUB_MEMORY SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID
59 #endif /* SOC_J721E */
60 
61 #if defined (SOC_J7200)
62 #define SDL_MCU_R5F0_SUB_MEMORY SDL_MCU_R5FSS0_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_RAM_ID
63 #endif /* SOC_J7200 */
64 
65 #if defined (SOC_J721S2)
66 #define SDL_MCU_R5F0_SUB_MEMORY SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_RAM_ID
67 #endif /* SOC_J721S2 */
68 
69 #if defined (SOC_J784S4)
70 #define SDL_MCU_R5F0_SUB_MEMORY SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_RAM_ID
71 #endif /* SOC_J784S4 */
72 
73 #ifdef __cplusplus
74 extern "C" {
75 #endif
76 
112 typedef enum {
113  SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
115  SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
117 } SDL_ECC_AggregatorType;
118 
119 
124 typedef enum {
126  SDL_INJECT_ECC_NO_ERROR = 0,
128  SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
130  SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
132  SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
134  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
136  SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
138  SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
140  SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
142  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
143 } SDL_ECC_InjectErrorType;
144 
145 
150 typedef enum {
151  SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
153  SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
155 } SDL_ECC_RamIdType;
156 
157 /* @} */
158 
169 typedef uint32_t SDL_ECC_MemType;
170 
171 #if defined (SOC_J721E)
172 
173  #define SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0u)
174  #define SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1u)
175  #define SDL_ECC_MEMTYPE_MCU_ADC0 (2u)
176  #define SDL_ECC_MEMTYPE_MCU_ADC1 (3u)
177  #define SDL_ECC_MEMTYPE_MCU_CPSW0 (4u)
178  #define SDL_ECC_MEMTYPE_MCU_FSS0_HPB0 (5u)
179  #define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0 (6u)
180  #define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1 (7u)
181 
182  #define SDL_ECC_MEMTYPE_MCU_MCAN0 (8u)
183  #define SDL_ECC_MEMTYPE_MCU_MCAN1 (9u)
184  #define SDL_ECC_MEMTYPE_MCU_MSRAM0 (10u)
185  #define SDL_ECC_MEMTYPE_MCU_NAVSS0 (11u)
186 
187  #define SDL_ECC_MEMTYPE_MCU_PSRAM0 (12u)
188  #define SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0 (13u)
189 
190  #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (14u)
191  #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (15u)
192  #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (16u)
193  #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (17u)
194  #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (18u)
195  #define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (19u)
196  #define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (20u)
197  #define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (21u)
198  #define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR (22u)
199  #define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR (23u)
200  #define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR (24u)
201  #define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR (25u)
202  #define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR (26u)
203  #define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR (27u)
204 
205  #define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR (28u)
206  #define SDL_PCIE0_ECC_AGGR_CORE_AXI_0 (29u)
207  #define SDL_PCIE0_ECC_AGGR_CORE_0 (30u)
208  #define SDL_PCIE1_ECC_AGGR_CORE_AXI_0 (31u)
209  #define SDL_PCIE1_ECC_AGGR_CORE_0 (32u)
210  #define SDL_PCIE2_ECC_AGGR_CORE_AXI_0 (33u)
211  #define SDL_PCIE2_ECC_AGGR_CORE_0 (34u)
212  #define SDL_PCIE3_ECC_AGGR_CORE_AXI_0 (35u)
213  #define SDL_PCIE3_ECC_AGGR_CORE_0 (36u)
214 
215  #define SDL_I3C0_I3C_S_ECC_AGGR (37u)
216  #define SDL_I3C0_I3C_P_ECC_AGGR (38u)
217  #define SDL_MCU_I3C0_I3C_P_ECC_AGGR (39u)
218  #define SDL_MCU_I3C0_I3C_S_ECC_AGGR (40u)
219  #define SDL_MCU_I3C1_I3C_P_ECC_AGGR (41u)
220  #define SDL_MCU_I3C1_I3C_S_ECC_AGGR (42u)
221  #define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR (43u)
222  #define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR (44u)
223 
224  #define SDL_CBASS_ECC_AGGR0 (45u)
225  #define SDL_MAIN_RC_ECC_AGGR0 (46u)
226 
227 
228  #define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR (47u)
229  #define SDL_DMPAC0_ECC_AGGR (48u)
230  #define SDL_MAIN_HC_ECC_AGGR0 (49u)
231  #define SDL_VPAC0_ECC_AGGR (50u)
232  #define SDL_VPAC0_VISS_ECC_AGGR (51u)
233  #define SDL_VPAC0_LDC_ECC_AGGR (52u)
234  #define SDL_R5FSS0_CORE0_ECC_AGGR (53u)
235  #define SDL_R5FSS1_CORE0_ECC_AGGR (54u)
236  #define SDL_R5FSS0_CORE1_ECC_AGGR (55u)
237  #define SDL_R5FSS1_CORE1_ECC_AGGR (56u)
238  #define SDL_NAVSS_VIRTSS_ECC_AGGR0 (57u)
239 
240  #define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (58u)
241  #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (59u)
242 
243  #define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR (60u)
244  #define SDL_MAIN_AC_ECC_AGGR0 (61u)
245 
246  #define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR (62u)
247  #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM (63u)
248  #define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM (64u)
249  #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (65u)
250  #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (66u)
251  #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (67u)
252  #define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (68u)
253  #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE (69u)
254  #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY (70u)
255  #define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC (71u)
256  #define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR (72u)
257  #define SDL_CSI_RX_IF0_ECC_AGGR_0 (73u)
258  #define SDL_CSI_RX_IF1_ECC_AGGR_0 (74u)
259  #define SDL_NAVSS0_MODSS_ECC_AGGR0 (75u)
260  #define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (76u)
261  #define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (77u)
262  #define SDL_NAVSS0_VIRTSS_ECC_AGGR0 (78u)
263  #define SDL_NAVSS0_NBSS_ECC_AGGR0 (79u)
264  #define SDL_IDOM1_ECC_AGGR0 (80u)
265  #define SDL_IDOM1_ECC_AGGR1 (81u)
266  #define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR (82u)
267  #define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR (83u)
268  #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR (84u)
269  #define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE (85u)
270  #define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR (86u)
271  #define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS (87u)
272  #define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0 (88u)
273  #define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR (89u)
274  #define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR (90u)
275  #define SDL_NAVSS0_UDMASS_ECC_AGGR0 (91u)
276 
277 
278  #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (92u)
279  #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (93u)
280  #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (94u)
281  #define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR (95u)
282  #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR (96u)
283  #define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR (97u)
284  #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_VBUS (98u)
285  #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CTL (99u)
286  #define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CFG (100u)
287  #define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR (101u)
288 
289 #define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR + 1U)
290 
291 
292 #endif
293 
294 #if defined (SOC_J7200)
295 
296 #define SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0u)
297 #define SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1u)
298 #define SDL_ECC_PDMA10_ECC_AGGR (2u)
299 #define SDL_ECC_PCIE1_1_ECC_AGGR (3u)
300 #define SDL_ECC_MCU_NAVSS0_0_ECC_AGGR (4u)
301 #define SDL_ECC_MCU_NAVSS0_1_ECC_AGGR (5u)
302 #define SDL_ECC_PCIE1_0_ECC_AGGR (6u)
303 #define SDL_ECC_USB0_ECC_AGGR (7u)
304 #define SDL_ECC_CPSW0_ECC_AGGR (8u)
305 #define SDL_ECC_MMCSD0_1_ECC_AGGR (9u)
306 #define SDL_ECC_MMCSD0_0_ECC_AGGR (10u)
307 #define SDL_ECC_MMCSD1_0_ECC_AGGR (11u)
308 #define SDL_ECC_MMCSD1_1_ECC_AGGR (12u)
309 #define SDL_ECC_MSRAM_512K0_ECC_AGGR (13u)
310 #define SDL_ECC_MCAN8_ECC_AGGR (14u)
311 #define SDL_ECC_MCAN9_ECC_AGGR (15u)
312 #define SDL_ECC_MCAN10_ECC_AGGR (16u)
313 #define SDL_ECC_MCAN11_ECC_AGGR (17u)
314 #define SDL_ECC_MCAN12_ECC_AGGR (18u)
315 #define SDL_ECC_MCAN13_ECC_AGGR (19u)
316 #define SDL_ECC_MCAN14_ECC_AGGR (20u)
317 #define SDL_ECC_MCAN15_ECC_AGGR (21u)
318 #define SDL_ECC_MCAN16_ECC_AGGR (22u)
319 #define SDL_ECC_MCAN17_ECC_AGGR (23u)
320 #define SDL_R5FSS0_CORE0_ECC_AGGR (24u)
321 #define SDL_ECC_I3C0_1_ECC_AGGR (25u)
322 #define SDL_ECC_I3C0_0_ECC_AGGR (26u)
323 #define SDL_ECC_MCAN0_ECC_AGGR (27u)
324 #define SDL_ECC_MCAN1_ECC_AGGR (28u)
325 #define SDL_ECC_MCAN2_ECC_AGGR (29u)
326 #define SDL_ECC_MCAN3_ECC_AGGR (30u)
327 #define SDL_ECC_MCAN4_ECC_AGGR (31u)
328 #define SDL_ECC_MCAN5_ECC_AGGR (32u)
329 #define SDL_ECC_MCAN6_ECC_AGGR (33u)
330 #define SDL_ECC_MCAN7_ECC_AGGR (34u)
331 #define SDL_ECC_IDOM0_ECC_AGGR16 (35u)
332 #define SDL_ECC_IDOM1_ECC_AGGR17 (36u)
333 #define SDL_ECC_VC_MAIN_RC_ECC_AGGR4_ECC_AGGR (37u)
334 #define SDL_ECC_VC_MAIN_HC_ECC_AGGR5_ECC_AGGR (38u)
335 #define SDL_ECC_VC_MAIN_SPI_G0_MAIN_0_ECCAGGR6 (39u)
336 #define SDL_ECC_VCL_NAVSS256_VIRTSS_PHYS_ECC_AGGR10_ECC_AGGR (40u)
337 #define SDL_ECC_VC_NAVSS256_NBSS_PHYS_ECC_AGGR11_ECC_AGGR (41u)
338 #define SDL_ECC_NAVSS0_0_ECC_AGGR (42u)
339 #define SDL_ECC_NAVSS0_1_ECC_AGGR (43u)
340 #define SDL_ECC_NAVSS0_3_ECC_AGGR (44u)
341 #define SDL_ECC_NAVSS0_2_ECC_AGGR (45u)
342 #define SDL_ECC_PDMA5_ECC_AGGR (46u)
343 #define SDL_ECC_PDMA9_ECC_AGGR (47u)
344 #define SDL_ECC_MCU_MCAN0_ECC_AGGR (48u)
345 #define SDL_ECC_MCU_MCAN1_ECC_AGGR (49u)
346 #define SDL_ECC_MCU_ADC0_ECC_AGGR (50u)
347 #define SDL_ECC_MCU_CPSW0_ECC_AGGR (51u)
348 #define SDL_ECC_MCU_MSRAM_1MB0_ECC_AGGR (52u)
349 #define SDL_ECC_MCU_SA2_UL0_ECC_AGGR (53u)
350 #define SDL_ECC_MCU_I3C0_1_ECC_AGGR (54u)
351 #define SDL_ECC_MCU_I3C0_0_ECC_AGGR (55u)
352 #define SDL_ECC_MCU_I3C1_1_ECC_AGGR (56u)
353 #define SDL_ECC_MCU_I3C1_0_ECC_AGGR (57u)
354 #define SDL_ECC_WKUP_VTM0_ECC_AGGR (58u)
355 #define SDL_ECC_MCU_FSS0_0_ECC_AGGR (59u)
356 #define SDL_ECC_MCU_FSS0_1_ECC_AGGR (60u)
357 #define SDL_ECC_MCU_VC_MCU_ECC_AGGR0 (61u)
358 #define SDL_R5FSS0_CORE1_ECC_AGGR (62u)
359 #define SDL_ECC_PSRAMECC0_ECC_AGGR (63u)
360 #define SDL_ECC_PSRAM2KECC0_ECC_AGGR (64u)
361 #define SDL_ECC_VCL_MAIN_INFRA_ECC_AGGR0_0_ECC_AGGR (65u)
362 
363 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (66u)
364 #define SDL_ECC_COMPUTE_CLUSTER0_2_ECC_AGGR (67u)
365 #define SDL_ECC_COMPUTE_CLUSTER0_4_ECC_AGGR (68u)
366 #define SDL_ECC_COMPUTE_CLUSTER0_5_ECC_AGGR (69u)
367 #define SDL_ECC_COMPUTE_CLUSTER0_1_ECC_AGGR (70u)
368 #define SDL_ECC_COMPUTE_CLUSTER0_0_ECC_AGGR (71u)
369 #define SDL_DDR0_0_ECC_AGGR (72u)
370 #define SDL_DDR0_1_ECC_AGGR (73u)
371 #define SDL_DDR0_2_ECC_AGGR (74u)
372 #define SDL_ECC_COMPUTE_CLUSTER0_6_ECC_AGGR (75u)
373 
374 
375 #define SDL_ECC_MEMTYPE_MAX (SDL_ECC_COMPUTE_CLUSTER0_6_ECC_AGGR + 1U)
376 
377 
378 /* Max entries based on max mem type */
379 #define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES (SDL_ECC_VCL_MAIN_INFRA_ECC_AGGR0_0_ECC_AGGR+1U)
380 
381 #define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDL_ECC_COMPUTE_CLUSTER0_6_ECC_AGGR - \
382  SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)
383 
384 #endif
385 
386 #if defined (SOC_J721S2)
387 
388 #define SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0U)
389 #define SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1U)
390 #define SDL_IVC_DOM1_ECC_AGGR17_ECC_AGGR (2U)
391 #define SDL_WKUP_VTM0_ECC_AGGR (3U)
392 #define SDL_MSRAM_512K0_ECC_AGGR (4U)
393 #define SDL_MSRAM_512K1_ECC_AGGR (5U)
394 #define SDL_PSRAMECC0_ECC_AGGR (6U)
395 #define SDL_MCU_MSRAM_1MB0_ECC_AGGR (7U)
396 #define SDL_ECC_AGGR4_ECC_AGGR (8U)
397 #define SDL_USB0_ECC_AGGR (9U)
398 #define SDL_MCU_I3C1_0_ECC_AGGR (10U)
399 #define SDL_MCU_I3C1_1_ECC_AGGR (11U)
400 #define SDL_VPAC0_0_ECC_AGGR (12U)
401 #define SDL_VPAC0_1_ECC_AGGR (13U)
402 #define SDL_VPAC0_ECC_AGGR (14U)
403 #define SDL_MCAN16_ECC_AGGR (15U)
404 #define SDL_PCIE1_0_ECC_AGGR (16U)
405 #define SDL_PCIE1_1_ECC_AGGR (17U)
406 #define SDL_IVC_DOM0_ECC_AGGR16_ECC_AGGR (18U)
407 #define SDL_PDMA6_ECC_AGGR (19U)
408 #define SDL_ECC_AGGR5_ECC_AGGR (20U)
409 #define SDL_DSS_DSI0_ECC_AGGR (21U)
410 #define SDL_ECC_AGGR0_ECC_AGGR (22U)
411 #define SDL_CSI_RX_IF0_ECC_AGGR (23U)
412 #define SDL_MCAN5_ECC_AGGR (24U)
413 #define SDL_PSRAM2KECC0_ECC_AGGR (25U)
414 #define SDL_PDMA7_ECC_AGGR (26U)
415 #define SDL_IVC_DOM0_ECC_AGGR18_ECC_AGGR (27U)
416 #define SDL_MCU_NAVSS0_0_ECC_AGGR (28U)
417 #define SDL_MCU_NAVSS0_1_ECC_AGGR (29U)
418 #define SDL_DSS_EDP0_2_ECC_AGGR (30U)
419 #define SDL_DSS_EDP0_0_ECC_AGGR (31U)
420 #define SDL_DSS_EDP0_1_ECC_AGGR (32U)
421 #define SDL_MCAN10_ECC_AGGR (33U)
422 #define SDL_SA2_UL0_ECC_AGGR (34U)
423 #define SDL_MMCSD0_0_ECC_AGGR (35U)
424 #define SDL_MMCSD0_1_ECC_AGGR (36U)
425 #define SDL_ECC_AGGR10_ECC_AGGR (37U)
426 #define SDL_CSI_TX_IF_V2_1_0_ECC_AGGR (38U)
427 #define SDL_CSI_TX_IF_V2_1_1_ECC_AGGR (39U)
428 #define SDL_CSI_TX_IF_V2_0_0_ECC_AGGR (40U)
429 #define SDL_CSI_TX_IF_V2_0_1_ECC_AGGR (41U)
430 #define SDL_MCU_MCAN0_ECC_AGGR (42U)
431 #define SDL_MCU_ADC12FCC1_ECC_AGGR (43U)
432 #define SDL_MCU_ADC12FCC0_ECC_AGGR (44U)
433 #define SDL_CSI_RX_IF1_ECC_AGGR (45U)
434 #define SDL_NAVSS0_0_ECC_AGGR (46U)
435 #define SDL_NAVSS0_1_ECC_AGGR (47U)
436 #define SDL_NAVSS0_2_ECC_AGGR (48U)
437 #define SDL_NAVSS0_3_ECC_AGGR (49U)
438 #define SDL_MAIN_IP_ECC_AGGR0_ECC_AGGR (50U)
439 #define SDL_MCU_MCAN1_ECC_AGGR (51U)
440 #define SDL_CPSW1_ECC_AGGR (52U)
441 #define SDL_MMCSD1_0_ECC_AGGR (53U)
442 #define SDL_MMCSD1_1_ECC_AGGR (54U)
443 #define SDL_MCUM_MCU_ECC_AGGR0_ECC_AGGR (55U)
444 #define SDL_MCU_FSS0_0_ECC_AGGR (56U)
445 #define SDL_MCU_FSS0_1_ECC_AGGR (57U)
446 #define SDL_MCU_FSS0_2_ECC_AGGR (58U)
447 #define SDL_WKUP_SMS0_TIFS_ECC_AGGR_0_ECC_AGGR (59U)
448 #define SDL_MCU_CPSW0_ECC_AGGR (60U)
449 #define SDL_MCU_I3C0_0_ECC_AGGR (61U)
450 #define SDL_MCU_I3C0_1_ECC_AGGR (62U)
451 #define SDL_R5FSS0_0_ECC_AGGR (63U)
452 #define SDL_R5FSS0_1_ECC_AGGR (64U)
453 #define SDL_R5FSS1_0_ECC_AGGR (65U)
454 #define SDL_R5FSS1_1_ECC_AGGR (66U)
455 #define SDL_DMPAC0_ECC_AGGR (67U)
456 #define SDL_ECC_AGGR9_ECC_AGGR (68U)
457 #define SDL_ECC_AGGR6_ECC_AGGR (69U)
458 #define SDL_MCAN9_ECC_AGGR (70U)
459 #define SDL_MCAN8_ECC_AGGR (71U)
460 #define SDL_MCAN1_ECC_AGGR (72U)
461 #define SDL_MCAN3_ECC_AGGR (73U)
462 #define SDL_MCAN2_ECC_AGGR (74U)
463 #define SDL_MCAN7_ECC_AGGR (75U)
464 #define SDL_MCAN6_ECC_AGGR (76U)
465 #define SDL_DSS_DSI1_ECC_AGGR (77U)
466 #define SDL_IVC_DOM1_ECC_AGGR19_ECC_AGGR (78U)
467 #define SDL_WKUP_SMS0_HSM_ECC_AGGR_0_ECC_AGGR (79U)
468 #define SDL_PDMA5_ECC_AGGR (80U)
469 #define SDL_MCAN11_ECC_AGGR (81U)
470 #define SDL_MCAN13_ECC_AGGR (82U)
471 #define SDL_MCAN12_ECC_AGGR (83U)
472 #define SDL_MCAN15_ECC_AGGR (84U)
473 #define SDL_MCAN14_ECC_AGGR (85U)
474 #define SDL_MCAN17_ECC_AGGR (86U)
475 #define SDL_MCAN0_ECC_AGGR (87U)
476 #define SDL_ECC_AGGR11_ECC_AGGR (88U)
477 #define SDL_MCAN4_ECC_AGGR (89U)
478 #define SDL_WKUP_ECC_AGGR0_ECC_AGGR (90U)
479 #define SDL_MCU_SA3_SS0_1_ECC_AGGR (91U)
480 
481 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (92U)
482 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (93U)
483 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (94U)
484 #define SDL_ECC_MEMTYPE_A72_COREPAC (95U)
485 #define SDL_ECC_MEMTYPE_A72_1 (96U)
486 #define SDL_ECC_MEMTYPE_C7X_1 (97U)
487 #define SDL_DDR0_0_ECC_AGGR (98U)
488 #define SDL_DDR1_0_ECC_AGGR (99U)
489 #define SDL_DDR0_1_ECC_AGGR (100U)
490 #define SDL_DDR1_1_ECC_AGGR (101U)
491 #define SDL_DDR0_2_ECC_AGGR (102U)
492 #define SDL_DDR1_2_ECC_AGGR (103U)
493 #define SDL_ECC_MEMTYPE_C7X_0 (104U)
494 #define SDL_ECC_MEMTYPE_A72_0 (105U)
495 #define SDL_ECC_MEMTYPE_GIC (106U)
496 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR3 (107U)
497 
498 #define SDL_ECC_MEMTYPE_MAX (SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR3 + 1U)
499 
500 /* Max entries based on max mem type */
501 #define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES (SDL_MCU_SA3_SS0_1_ECC_AGGR+1U)
502 
503 #define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR3 - \
504  SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)
505 
506 #endif
507 
508 #if defined (SOC_J784S4)
509 
510 #define SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0U) /* MCU_R5FSS0_0 */
511 #define SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1U) /* MCU_R5FSS0_1 */
512 #define SDL_PCIE0_0_ECC_AGGR (2U)
513 #define SDL_PCIE0_1_ECC_AGGR (3U)
514 #define SDL_PCIE3_0_ECC_AGGR (4U)
515 #define SDL_PCIE3_1_ECC_AGGR (5U)
516 #define SDL_PCIE2_0_ECC_AGGR (6U)
517 #define SDL_PCIE2_1_ECC_AGGR (7U)
518 #define SDL_MCU_CPSW0_ECC_AGGR (8U)
519 #define SDL_WKUP_SMS0_TIFS_ECC_AGGR_0_ECC_AGGR (9U)
520 #define SDL_WKUP_SMS0_HSM_ECC_AGGR_0_ECC_AGGR (10U)
521 #define SDL_MSRAM_512K1_ECC_AGGR (11U)
522 #define SDL_MSRAM_512K2_ECC_AGGR (12U)
523 #define SDL_PDMA6_ECC_AGGR (13U)
524 #define SDL_DSS_DSI0_ECC_AGGR (14U)
525 #define SDL_MCU_MSRAM_1MB0_ECC_AGGR (15U)
526 #define SDL_ECC_AGGR4_ECC_AGGR (16U)
527 #define SDL_USB0_ECC_AGGR (17U)
528 #define SDL_VPAC1_0_ECC_AGGR (18U)
529 #define SDL_VPAC1_1_ECC_AGGR (19U)
530 #define SDL_VPAC1_2_ECC_AGGR (20U)
531 #define SDL_ECC_AGGR6_ECC_AGGR (21U)
532 #define SDL_MCAN16_ECC_AGGR (22U)
533 #define SDL_UFS0_ECC_AGGR (23U)
534 #define SDL_IVC_DOM0_ECC_AGGR20_ECC_AGGR (24U)
535 #define SDL_PCIE1_0_ECC_AGGR (25U)
536 #define SDL_PCIE1_1_ECC_AGGR (26U)
537 #define SDL_ECC_AGGR5_ECC_AGGR (27U)
538 #define SDL_IVC_DOM0_ECC_AGGR16_ECC_AGGR (28U)
539 #define SDL_VPAC0_0_ECC_AGGR (29U)
540 #define SDL_VPAC0_1_ECC_AGGR (30U)
541 #define SDL_VPAC0_2_ECC_AGGR (31U)
542 #define SDL_MCU_MCAN0_ECC_AGGR (32U)
543 #define SDL_PSRAMECC0_ECC_AGGR (33U)
544 #define SDL_MCU_MCAN1_ECC_AGGR (34U)
545 #define SDL_MCU_SA3_SS0_0_ECC_AGGR (35U)
546 #define SDL_MCU_SA3_SS0_1_ECC_AGGR (36U)
547 #define SDL_MMCSD1_0_ECC_AGGR (37U)
548 #define SDL_MMCSD1_1_ECC_AGGR (38U)
549 #define SDL_MCAN4_ECC_AGGR (39U)
550 #define SDL_IVC_DOM1_ECC_AGGR21_ECC_AGGR (40U)
551 #define SDL_IVC_DOM1_ECC_AGGR17_ECC_AGGR (41U)
552 #define SDL_MCU_I3C1_0_ECC_AGGR (42U)
553 #define SDL_MCU_I3C1_1_ECC_AGGR (43U)
554 #define SDL_ECC_AGGR0_ECC_AGGR (44U)
555 #define SDL_CSI_RX_IF2_ECC_AGGR (45U)
556 #define SDL_CSI_RX_IF1_ECC_AGGR (46U)
557 #define SDL_CSI_RX_IF0_ECC_AGGR (47U)
558 #define SDL_PSRAM2KECC0_ECC_AGGR (48U)
559 #define SDL_PDMA7_ECC_AGGR (49U)
560 #define SDL_ECC_AGGR11_ECC_AGGR (50U)
561 #define SDL_IVC_DOM0_ECC_AGGR18_ECC_AGGR (51U)
562 #define SDL_MCU_NAVSS0_0_ECC_AGGR (52U)
563 #define SDL_MCU_NAVSS0_1_ECC_AGGR (53U)
564 #define SDL_DSS_EDP0_0_ECC_AGGR (54U)
565 #define SDL_DSS_EDP0_1_ECC_AGGR (55U)
566 #define SDL_DSS_EDP0_2_ECC_AGGR (56U)
567 #define SDL_MCAN10_ECC_AGGR (57U)
568 #define SDL_SA2_UL0_ECC_AGGR (58U)
569 #define SDL_MMCSD0_0_ECC_AGGR (59U)
570 #define SDL_MMCSD0_1_ECC_AGGR (60U)
571 #define SDL_ECC_AGGR10_ECC_AGGR (61U)
572 #define SDL_CSI_TX_IF_V2_1_0_ECC_AGGR (62U)
573 #define SDL_CSI_TX_IF_V2_1_1_ECC_AGGR (63U)
574 #define SDL_CSI_TX_IF_V2_0_0_ECC_AGGR (64U)
575 #define SDL_CSI_TX_IF_V2_0_1_ECC_AGGR (65U)
576 #define SDL_NAVSS0_0_ECC_AGGR (66U)
577 #define SDL_NAVSS0_1_ECC_AGGR (67U)
578 #define SDL_NAVSS0_2_ECC_AGGR (68U)
579 #define SDL_NAVSS0_3_ECC_AGGR (69U)
580 #define SDL_MCU_ADC12FCC1_ECC_AGGR (70U)
581 #define SDL_MCU_ADC12FCC0_ECC_AGGR (71U)
582 #define SDL_MCAN14_ECC_AGGR (72U)
583 #define SDL_MAIN_IP_ECC_AGGR0_ECC_AGGR (73U)
584 #define SDL_WKUP_VTM0_ECC_AGGR (74U)
585 #define SDL_MSRAM_512K0_ECC_AGGR (75U)
586 #define SDL_CPSW1_ECC_AGGR (76U)
587 #define SDL_MCUM_MCU_ECC_AGGR0_ECC_AGGR (77U)
588 #define SDL_MCU_FSS0_0_ECC_AGGR (78U)
589 #define SDL_MCU_FSS0_1_ECC_AGGR (79U)
590 #define SDL_MCU_FSS0_2_ECC_AGGR (80U)
591 #define SDL_MCU_I3C0_0_ECC_AGGR (81U)
592 #define SDL_MCU_I3C0_1_ECC_AGGR (82U)
593 #define SDL_R5FSS0_0_ECC_AGGR (83U)
594 #define SDL_R5FSS0_1_ECC_AGGR (84U)
595 #define SDL_R5FSS1_0_ECC_AGGR (85U)
596 #define SDL_R5FSS1_1_ECC_AGGR (86U)
597 #define SDL_R5FSS2_0_ECC_AGGR (87U)
598 #define SDL_R5FSS2_1_ECC_AGGR (88U)
599 #define SDL_PDMA5_ECC_AGGR (89U)
600 #define SDL_MCAN5_ECC_AGGR (90U)
601 #define SDL_MCAN9_ECC_AGGR (91U)
602 #define SDL_MCAN8_ECC_AGGR (92U)
603 #define SDL_MCAN1_ECC_AGGR (93U)
604 #define SDL_MCAN3_ECC_AGGR (94U)
605 #define SDL_MCAN2_ECC_AGGR (95U)
606 #define SDL_MCAN7_ECC_AGGR (96U)
607 #define SDL_MCAN6_ECC_AGGR (97U)
608 #define SDL_DSS_DSI1_ECC_AGGR (98U)
609 #define SDL_IVC_DOM1_ECC_AGGR19_ECC_AGGR (99U)
610 #define SDL_MCAN11_ECC_AGGR (100U)
611 #define SDL_MCAN13_ECC_AGGR (101U)
612 #define SDL_MCAN12_ECC_AGGR (102U)
613 #define SDL_MCAN15_ECC_AGGR (103U)
614 #define SDL_MCAN17_ECC_AGGR (104U)
615 #define SDL_ECC_AGGR9_ECC_AGGR (105U)
616 #define SDL_MCAN0_ECC_AGGR (106U)
617 #define SDL_WKUP_ECC_AGGR0_ECC_AGGR (107U)
618 #define SDL_DMPAC0_ECC_AGGR (108U)
619 #define SDL_CPSW_9XUSSM0_ECC_AGGR (109U)
620 
621 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (110U)
622 #define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (111U)
623 #define SDL_COMPUTE_CLUSTER0_MSMC_DDR_0_ECC2_AGGR (112U)
624 #define SDL_COMPUTE_CLUSTER0_MSMC_DDR_1_ECC3_AGGR (113U)
625 #define SDL_COMPUTE_CLUSTER0_MSMC_DDR_2_ECC4_AGGR (114U)
626 #define SDL_COMPUTE_CLUSTER0_MSMC_DDR_3_ECC5_AGGR (115U)
627 #define SDL_COMPUTE_CLUSTER0_GICSS_ECC_AGGR (116U)
628 #define SDL_COMPUTE_CLUSTER0_AW4_ECC0_AGGR (117U)
629 #define SDL_COMPUTE_CLUSTER0_AW4_ECC1_AGGR (118U)
630 #define SDL_COMPUTE_CLUSTER0_DSP0_ECC_AGGR (119U)
631 #define SDL_DDR0_0_ECC_AGGR (120U)
632 #define SDL_DDR0_1_ECC_AGGR (121U)
633 #define SDL_DDR0_2_ECC_AGGR (122U)
634 #define SDL_DDR1_0_ECC_AGGR (123U)
635 #define SDL_DDR1_1_ECC_AGGR (124U)
636 #define SDL_DDR1_2_ECC_AGGR (125U)
637 #define SDL_DDR2_0_ECC_AGGR (126U)
638 #define SDL_DDR2_1_ECC_AGGR (127U)
639 #define SDL_DDR2_2_ECC_AGGR (128U)
640 #define SDL_DDR3_0_ECC_AGGR (129U)
641 #define SDL_DDR3_1_ECC_AGGR (130U)
642 #define SDL_DDR3_2_ECC_AGGR (131U)
643 #define SDL_COMPUTE_CLUSTER0_MSMC2_ECC_AGGR0_AGGR (132U)
644 #define SDL_COMPUTE_CLUSTER0_MSMC2_ECC_AGGR1_AGGR (133U)
645 #define SDL_COMPUTE_CLUSTER0_AW5_ECC0_BASE (134U)
646 #define SDL_COMPUTE_CLUSTER0_AW5_ECC1_BASE (135U)
647 #define SDL_COMPUTE_CLUSTER0_DSP1_ECC_AGGR (136U)
648 #define SDL_COMPUTE_CLUSTER0_AW6_ECC0_AGGR (137U)
649 #define SDL_COMPUTE_CLUSTER0_AW6_ECC1_AGGR (138U)
650 #define SDL_COMPUTE_CLUSTER0_DSP2_ECC_AGGR (139U)
651 #define SDL_COMPUTE_CLUSTER0_AW7_ECC0_AGGR (140U)
652 #define SDL_COMPUTE_CLUSTER0_AW7_ECC1_AGGR (141U)
653 #define SDL_COMPUTE_CLUSTER0_AW7_DSP_ECC_AGGR (142U)
654 #define SDL_COMPUTE_CLUSTER0_CFG0_ARM_COREPAC_ECC_AGGR (143U)
655 #define SDL_COMPUTE_CLUSTER0_CFG0_ARM_CORE0_ECC_AGGR (144U)
656 #define SDL_COMPUTE_CLUSTER0_CFG0_ARM_CORE1_ECC_AGGR (145U)
657 #define SDL_COMPUTE_CLUSTER0_CFG0_ARM_CORE2_ECC_AGGR (146U)
658 #define SDL_COMPUTE_CLUSTER0_CFG0_ARM_CORE3_ECC_AGGR (147U)
659 #define SDL_COMPUTE_CLUSTER0_CFG1_ARM_COREPAC_ECC_AGGR (148U)
660 #define SDL_COMPUTE_CLUSTER0_CFG1_ARM_CORE0_ECC_AGGR (149U)
661 #define SDL_COMPUTE_CLUSTER0_CFG1_ARM_CORE1_ECC_AGGR (150U)
662 #define SDL_COMPUTE_CLUSTER0_CFG1_ARM_CORE2_ECC_AGGR (151U)
663 #define SDL_COMPUTE_CLUSTER0_CFG1_ARM_CORE3_ECC_AGGR (152U)
664 
665 #define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_CFG1_ARM_CORE3_ECC_AGGR + 1U)
666 
667 /* Max entries based on max mem type */
668 #define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES (SDL_CPSW_9XUSSM0_ECC_AGGR+1U)
669 
670 #define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDL_COMPUTE_CLUSTER0_CFG1_ARM_CORE3_ECC_AGGR - \
671  SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)
672 
673 #endif
674 
679 typedef uint32_t SDL_ECC_MemSubType;
680 
681 #if defined (SOC_J721E)
682 
683 /* The following are the memory sub type for Memory type
684  SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
685 /* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */
686 
688 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
689 
690 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
691 
692 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
693 
694 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
695 
696 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
697 
698 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
699 
700 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
701 
702 #endif
703 
704 #if defined (SOC_J7200)
705 
706 /* The following are the memory sub type for Memory type
707  SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
708 /* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */
709 
711 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_ATCM0_BANK0_RAM_ID)
712 
713 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_ATCM0_BANK1_RAM_ID)
714 
715 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
716 
717 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
718 
719 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
720 
721 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
722 
723 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_CPU0_KS_VIM_RAMECC_RAM_ID)
724 
725 #endif
726 
727 #if defined (SOC_J721S2) || defined (SOC_J784S4)
728 
729 /* The following are the memory sub type for Memory type
730  SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
731 /* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */
732 
734 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
735 
736 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
737 
738 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
739 
740 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
741 
742 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
743 
744 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
745 
746 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
747 
748 #endif
749 
751 typedef void (*SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);
752 
754 typedef void (*SDL_ECC_VIMDEDVector_t) (void);
755 
756 /* @} */
757 
767 typedef struct SDL_ECC_InitConfig_s
768 {
769  uint32_t numRams;
772  SDL_ECC_MemSubType *pMemSubTypeList;
774 } SDL_ECC_InitConfig_t;
775 
780 typedef struct SDL_ECC_InjectErrorConfig_s
781 {
782  uint32_t *pErrMem;
784  uint64_t errMem64;
786  uint32_t flipBitMask;
788  uint32_t chkGrp;
790 } SDL_ECC_InjectErrorConfig_t;
791 
796 typedef struct SDL_ECC_ErrorInfo_s
797 {
798  SDL_ECC_MemType eccMemType;
800  SDL_ECC_MemSubType memSubType;
802  SDL_Ecc_AggrIntrSrc intrSrc;
804  uint32_t bitErrCnt;
806  uint32_t injectBitErrCnt;
808  uint32_t bitErrorGroup;
810  uint64_t bitErrorOffset;
812 } SDL_ECC_ErrorInfo_t;
813 
814 /* @} */
815 
829 int32_t SDL_ECC_initEsm (const SDL_ESM_Inst esmInstType);
830 
840 int32_t SDL_ECC_init (SDL_ECC_MemType eccMemType,
841  const SDL_ECC_InitConfig_t *pECCInitConfig);
842 
853 int32_t SDL_ECC_initMemory (SDL_ECC_MemType eccMemType,
854  SDL_ECC_MemSubType memSubType);
855 
869 int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType,
870  SDL_ECC_MemSubType memSubType,
871  SDL_ECC_InjectErrorType errorType,
872  const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig,
873  uint32_t selfTestTimeOut);
874 
887 int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType,
888  SDL_ECC_MemSubType memSubType,
889  SDL_ECC_InjectErrorType errorType,
890  const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig);
891 
901 int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType,
902  SDL_ECC_staticRegs *pStaticRegs);
903 
915 int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType,
916  SDL_Ecc_AggrIntrSrc intrSrc,
917  SDL_ECC_ErrorInfo_t *pErrorInfo);
918 
928 int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType,
929  SDL_Ecc_AggrIntrSrc intrSrc);
930 
944 int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc,
945  SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType);
946 
960 int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType,
961  SDL_Ecc_AggrIntrSrc intrSrc,
962  SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents);
963 
975 void SDL_ECC_registerVIMDEDHandler(SDL_ECC_VIMDEDVector_t VIMDEDHandler);
976 
995 void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
996  uint32_t errorSrc,
997  uint32_t address,
998  uint32_t ramId,
999  uint64_t bitErrorOffset,
1000  uint32_t bitErrorGroup);
1001 
1002 /* @} */
1003 
1004 #ifdef __cplusplus
1005 }
1006 #endif /* extern "C" */
1007 
1008 #endif /* INCLUDE_SDL_ECC_H_ */
SDL_ECC_AggregatorType
SDL_ECC_AggregatorType
This enumerator defines the different ECC aggregator types.
Definition: sdl_ecc.h:112
SDL_ECC_init
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
SDL_ESM_Inst
SDL_ESM_Inst
Defines the different ESM instance types
Definition: ip/sdl_esm.h:167
SDL_ECC_initMemory
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
SDL_Ecc_AggrEDCErrorSubType
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: sdl_ip_ecc.h:187
SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE
Definition: sdl_ecc.h:134
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
Definition: sdl_ecc.h:128
SDL_ECC_getESMErrorInfo
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC ...
SDL_ECC_ErrorInfo_t::bitErrorGroup
uint32_t bitErrorGroup
Definition: sdl_ecc.h:808
SDL_ECC_ErrorInfo_t::memSubType
SDL_ECC_MemSubType memSubType
Definition: sdl_ecc.h:800
SDL_ECC_applicationCallbackFunction
void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType, uint32_t errorSrc, uint32_t address, uint32_t ramId, uint64_t bitErrorOffset, uint32_t bitErrorGroup)
Application provided external callback function for ECC handling Called inside the reference function...
SDL_ECC_InjectErrorConfig_t::chkGrp
uint32_t chkGrp
Definition: sdl_ecc.h:788
SDL_ECC_InjectErrorConfig_t
This structure defines the inject error configuration.
Definition: sdl_ecc.h:780
SDL_ECC_initEsm
int32_t SDL_ECC_initEsm(const SDL_ESM_Inst esmInstType)
Initializes an module for usage with ECC module.
SDL_ECC_ErrorInfo_t::intrSrc
SDL_Ecc_AggrIntrSrc intrSrc
Definition: sdl_ecc.h:802
SDL_ECC_injectError
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
SDL_ECC_AGGR_TYPE_FULL_FUNCTION
Definition: sdl_ecc.h:115
SDL_ECC_staticRegs
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: sdl_ip_ecc.h:348
SDL_ECC_InitConfig_t::numRams
uint32_t numRams
Definition: sdl_ecc.h:769
SDL_ECC_ErrorInfo_t
This structure defines the error status information.
Definition: sdl_ecc.h:796
SDL_ECC_RamIdType
SDL_ECC_RamIdType
This enumerator defines the different ECC RAM ID types.
Definition: sdl_ecc.h:150
SDL_ECC_MemType
uint32_t SDL_ECC_MemType
This enumerator indicate ECC memory type.
Definition: sdl_ecc.h:169
SDL_ECC_getErrorInfo
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
Retrieves the ECC error information for the specified memtype and interrupt source.
SDL_ECC_InitConfig_t::pMemSubTypeList
SDL_ECC_MemSubType * pMemSubTypeList
Definition: sdl_ecc.h:772
SDL_ECC_ErrorInfo_t::bitErrorOffset
uint64_t bitErrorOffset
Definition: sdl_ecc.h:810
SDL_ECC_registerVIMDEDHandler
void SDL_ECC_registerVIMDEDHandler(SDL_ECC_VIMDEDVector_t VIMDEDHandler)
Register Handler for VIM DED ECC error.
SDL_ECC_InitConfig_t
This structure defines the elements of ECC Init configuration.
Definition: sdl_ecc.h:767
SDL_ECC_ackIntr
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
Acknowledge the ECC interrupt.
SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE
Definition: sdl_ecc.h:132
SDL_ECC_RAM_ID_TYPE_WRAPPER
Definition: sdl_ecc.h:151
SDL_ECC_InjectErrorConfig_t::flipBitMask
uint32_t flipBitMask
Definition: sdl_ecc.h:786
SDL_ECC_selfTest
int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig, uint32_t selfTestTimeOut)
Runs self test by injecting and error and monitor response Assumes ECC is already enabled.
SDL_ECC_InjectErrorConfig_t::errMem64
uint64_t errMem64
Definition: sdl_ecc.h:784
SDL_ECC_VIMDEDVector_t
void(* SDL_ECC_VIMDEDVector_t)(void)
Definition: sdl_ecc.h:754
sdl_esm.h
Header file contains enumerations, structure definitions and function declarations for SDL Error Sign...
SDL_ECC_InjectErrorConfig_t::pErrMem
uint32_t * pErrMem
Definition: sdl_ecc.h:782
SDL_ECC_MemSubType
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:679
SDL_ECC_ErrorInfo_t::eccMemType
SDL_ECC_MemType eccMemType
Definition: sdl_ecc.h:798
SDL_ECC_clearNIntrPending
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
Clears N pending interrupts for the specified memtype, subtype and interrupt source.
SDL_ECC_AGGR_TYPE_INJECT_ONLY
Definition: sdl_ecc.h:113
SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:142
SDL_INJECT_ECC_NO_ERROR
Definition: sdl_ecc.h:126
SDL_Ecc_AggrIntrSrc
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: sdl_ip_ecc.h:106
SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:140
SDL_ECC_getStaticRegisters
int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType, SDL_ECC_staticRegs *pStaticRegs)
Gets the static registers for the specified ECC instance.
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
Definition: sdl_ecc.h:130
SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT
Definition: sdl_ecc.h:138
SDL_ECC_ErrorInfo_t::bitErrCnt
uint32_t bitErrCnt
Definition: sdl_ecc.h:804
SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT
Definition: sdl_ecc.h:136
SDL_ECC_RAM_ID_TYPE_INTERCONNECT
Definition: sdl_ecc.h:153
SDL_ECC_ErrorCallback_t
void(* SDL_ECC_ErrorCallback_t)(uint32_t errorSrc, uint32_t address)
Definition: sdl_ecc.h:751
SDL_ECC_InjectErrorType
SDL_ECC_InjectErrorType
ECC Inject error types.
Definition: sdl_ecc.h:124
SDL_ECC_ErrorInfo_t::injectBitErrCnt
uint32_t injectBitErrCnt
Definition: sdl_ecc.h:806