Data Structures
struct	SDL_ecc_ramRegs

Macros
#define	SDL_ECC_RAM_WRAP_REV (0x00000010U)

#define	SDL_ECC_RAM_CTRL (0x00000014U)

#define	SDL_ECC_RAM_ERR_CTRL1 (0x00000018U)

#define	SDL_ECC_RAM_ERR_CTRL2 (0x0000001CU)

#define	SDL_ECC_RAM_ERR_STAT1 (0x00000020U)

#define	SDL_ECC_RAM_ERR_STAT2 (0x00000024U)

#define	SDL_ECC_RAM_ERR_STAT3 (0x00000028U)

#define	SDL_ECC_RAM_WRAP_REV_SCHEME_MASK (0xC0000000U)

#define	SDL_ECC_RAM_WRAP_REV_SCHEME_SHIFT (0x0000001EU)

#define	SDL_ECC_RAM_WRAP_REV_SCHEME_MAX (0x00000003U)

#define	SDL_ECC_RAM_WRAP_REV_BU_MASK (0x30000000U)

#define	SDL_ECC_RAM_WRAP_REV_BU_SHIFT (0x0000001CU)

#define	SDL_ECC_RAM_WRAP_REV_BU_MAX (0x00000003U)

#define	SDL_ECC_RAM_WRAP_REV_MODULE_ID_MASK (0x0FFF0000U)

#define	SDL_ECC_RAM_WRAP_REV_MODULE_ID_SHIFT (0x00000010U)

#define	SDL_ECC_RAM_WRAP_REV_MODULE_ID_MAX (0x00000FFFU)

#define	SDL_ECC_RAM_WRAP_REV_REVRTL_MASK (0x0000F800U)

#define	SDL_ECC_RAM_WRAP_REV_REVRTL_SHIFT (0x0000000BU)

#define	SDL_ECC_RAM_WRAP_REV_REVRTL_MAX (0x0000001FU)

#define	SDL_ECC_RAM_WRAP_REV_REVMAJ_MASK (0x00000700U)

#define	SDL_ECC_RAM_WRAP_REV_REVMAJ_SHIFT (0x00000008U)

#define	SDL_ECC_RAM_WRAP_REV_REVMAJ_MAX (0x00000007U)

#define	SDL_ECC_RAM_WRAP_REV_CUSTOM_MASK (0x000000C0U)

#define	SDL_ECC_RAM_WRAP_REV_CUSTOM_SHIFT (0x00000006U)

#define	SDL_ECC_RAM_WRAP_REV_CUSTOM_MAX (0x00000003U)

#define	SDL_ECC_RAM_WRAP_REV_REVMIN_MASK (0x0000003FU)

#define	SDL_ECC_RAM_WRAP_REV_REVMIN_SHIFT (0x00000000U)

#define	SDL_ECC_RAM_WRAP_REV_REVMIN_MAX (0x0000003FU)

#define	SDL_ECC_RAM_CTRL_ECC_ENABLE_MASK (0x00000001U)

#define	SDL_ECC_RAM_CTRL_ECC_ENABLE_SHIFT (0x00000000U)

#define	SDL_ECC_RAM_CTRL_ECC_ENABLE_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_ECC_CHECK_MASK (0x00000002U)

#define	SDL_ECC_RAM_CTRL_ECC_CHECK_SHIFT (0x00000001U)

#define	SDL_ECC_RAM_CTRL_ECC_CHECK_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_ENABLE_RMW_MASK (0x00000004U)

#define	SDL_ECC_RAM_CTRL_ENABLE_RMW_SHIFT (0x00000002U)

#define	SDL_ECC_RAM_CTRL_ENABLE_RMW_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_FORCE_SEC_MASK (0x00000008U)

#define	SDL_ECC_RAM_CTRL_FORCE_SEC_SHIFT (0x00000003U)

#define	SDL_ECC_RAM_CTRL_FORCE_SEC_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_FORCE_DED_MASK (0x00000010U)

#define	SDL_ECC_RAM_CTRL_FORCE_DED_SHIFT (0x00000004U)

#define	SDL_ECC_RAM_CTRL_FORCE_DED_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_FORCE_N_ROW_MASK (0x00000020U)

#define	SDL_ECC_RAM_CTRL_FORCE_N_ROW_SHIFT (0x00000005U)

#define	SDL_ECC_RAM_CTRL_FORCE_N_ROW_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_ERROR_ONCE_MASK (0x00000040U)

#define	SDL_ECC_RAM_CTRL_ERROR_ONCE_SHIFT (0x00000006U)

#define	SDL_ECC_RAM_CTRL_ERROR_ONCE_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_CHECK_PARITY_MASK (0x00000080U)

#define	SDL_ECC_RAM_CTRL_CHECK_PARITY_SHIFT (0x00000007U)

#define	SDL_ECC_RAM_CTRL_CHECK_PARITY_MAX (0x00000001U)

#define	SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MASK (0x00000100U)

#define	SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_SHIFT (0x00000008U)

#define	SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MAX (0x00000001U)

#define	SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MASK (0xFFFFFFFFU)

#define	SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_SHIFT (0x00000000U)

#define	SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MAX (0xFFFFFFFFU)

#define	SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MASK (0x0000FFFFU)

#define	SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_SHIFT (0x00000000U)

#define	SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MAX (0x0000FFFFU)

#define	SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MASK (0xFFFF0000U)

#define	SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_SHIFT (0x00000010U)

#define	SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MAX (0x0000FFFFU)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MASK (0x00000003U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_SEC_SHIFT (0x00000000U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MAX (0x00000003U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_DED_MASK (0x0000000CU)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_DED_SHIFT (0x00000002U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_DED_MAX (0x00000003U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MASK (0x00000010U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_SHIFT (0x00000004U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MAX (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MASK (0x00000060U)

#define	SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_SHIFT (0x00000005U)

#define	SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MAX (0x00000003U)

#define	SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MASK (0x00000080U)

#define	SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_SHIFT (0x00000007U)

#define	SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MAX (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MASK (0x00000300U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_SHIFT (0x00000008U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MAX (0x00000003U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MASK (0x00000C00U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_SHIFT (0x0000000AU)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MAX (0x00000003U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MASK (0x00001000U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_SHIFT (0x0000000CU)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MAX (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MASK (0x00006000U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_SHIFT (0x0000000DU)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MAX (0x00000003U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MASK (0x00008000U)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_SHIFT (0x0000000FU)

#define	SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MAX (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MASK (0xFFFF0000U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_SHIFT (0x00000010U)

#define	SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MAX (0x0000FFFFU)

#define	SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MASK (0xFFFFFFFFU)

#define	SDL_ECC_RAM_ERR_STAT2_ECC_ROW_SHIFT (0x00000000U)

#define	SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MAX (0xFFFFFFFFU)

#define	SDL_ECC_RAM_ERR_STAT3_WB_PEND_MASK (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT3_WB_PEND_SHIFT (0x00000000U)

#define	SDL_ECC_RAM_ERR_STAT3_WB_PEND_MAX (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MASK (0x00000002U)

#define	SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_SHIFT (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)

#define	SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MASK (0x00000200U)

#define	SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_SHIFT (0x00000009U)

#define	SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)

Macro Definition Documentation

◆ SDL_ECC_RAM_WRAP_REV

#define SDL_ECC_RAM_WRAP_REV (0x00000010U)

◆ SDL_ECC_RAM_CTRL

#define SDL_ECC_RAM_CTRL (0x00000014U)

◆ SDL_ECC_RAM_ERR_CTRL1

#define SDL_ECC_RAM_ERR_CTRL1 (0x00000018U)

◆ SDL_ECC_RAM_ERR_CTRL2

#define SDL_ECC_RAM_ERR_CTRL2 (0x0000001CU)

◆ SDL_ECC_RAM_ERR_STAT1

#define SDL_ECC_RAM_ERR_STAT1 (0x00000020U)

◆ SDL_ECC_RAM_ERR_STAT2

#define SDL_ECC_RAM_ERR_STAT2 (0x00000024U)

◆ SDL_ECC_RAM_ERR_STAT3

#define SDL_ECC_RAM_ERR_STAT3 (0x00000028U)

◆ SDL_ECC_RAM_WRAP_REV_SCHEME_MASK

#define SDL_ECC_RAM_WRAP_REV_SCHEME_MASK (0xC0000000U)

◆ SDL_ECC_RAM_WRAP_REV_SCHEME_SHIFT

#define SDL_ECC_RAM_WRAP_REV_SCHEME_SHIFT (0x0000001EU)

◆ SDL_ECC_RAM_WRAP_REV_SCHEME_MAX

#define SDL_ECC_RAM_WRAP_REV_SCHEME_MAX (0x00000003U)

◆ SDL_ECC_RAM_WRAP_REV_BU_MASK

#define SDL_ECC_RAM_WRAP_REV_BU_MASK (0x30000000U)

◆ SDL_ECC_RAM_WRAP_REV_BU_SHIFT

#define SDL_ECC_RAM_WRAP_REV_BU_SHIFT (0x0000001CU)

◆ SDL_ECC_RAM_WRAP_REV_BU_MAX

#define SDL_ECC_RAM_WRAP_REV_BU_MAX (0x00000003U)

◆ SDL_ECC_RAM_WRAP_REV_MODULE_ID_MASK

#define SDL_ECC_RAM_WRAP_REV_MODULE_ID_MASK (0x0FFF0000U)

◆ SDL_ECC_RAM_WRAP_REV_MODULE_ID_SHIFT

#define SDL_ECC_RAM_WRAP_REV_MODULE_ID_SHIFT (0x00000010U)

◆ SDL_ECC_RAM_WRAP_REV_MODULE_ID_MAX

#define SDL_ECC_RAM_WRAP_REV_MODULE_ID_MAX (0x00000FFFU)

◆ SDL_ECC_RAM_WRAP_REV_REVRTL_MASK

#define SDL_ECC_RAM_WRAP_REV_REVRTL_MASK (0x0000F800U)

◆ SDL_ECC_RAM_WRAP_REV_REVRTL_SHIFT

#define SDL_ECC_RAM_WRAP_REV_REVRTL_SHIFT (0x0000000BU)

◆ SDL_ECC_RAM_WRAP_REV_REVRTL_MAX

#define SDL_ECC_RAM_WRAP_REV_REVRTL_MAX (0x0000001FU)

◆ SDL_ECC_RAM_WRAP_REV_REVMAJ_MASK

#define SDL_ECC_RAM_WRAP_REV_REVMAJ_MASK (0x00000700U)

◆ SDL_ECC_RAM_WRAP_REV_REVMAJ_SHIFT

#define SDL_ECC_RAM_WRAP_REV_REVMAJ_SHIFT (0x00000008U)

◆ SDL_ECC_RAM_WRAP_REV_REVMAJ_MAX

#define SDL_ECC_RAM_WRAP_REV_REVMAJ_MAX (0x00000007U)

◆ SDL_ECC_RAM_WRAP_REV_CUSTOM_MASK

#define SDL_ECC_RAM_WRAP_REV_CUSTOM_MASK (0x000000C0U)

◆ SDL_ECC_RAM_WRAP_REV_CUSTOM_SHIFT

#define SDL_ECC_RAM_WRAP_REV_CUSTOM_SHIFT (0x00000006U)

◆ SDL_ECC_RAM_WRAP_REV_CUSTOM_MAX

#define SDL_ECC_RAM_WRAP_REV_CUSTOM_MAX (0x00000003U)

◆ SDL_ECC_RAM_WRAP_REV_REVMIN_MASK

#define SDL_ECC_RAM_WRAP_REV_REVMIN_MASK (0x0000003FU)

◆ SDL_ECC_RAM_WRAP_REV_REVMIN_SHIFT

#define SDL_ECC_RAM_WRAP_REV_REVMIN_SHIFT (0x00000000U)

◆ SDL_ECC_RAM_WRAP_REV_REVMIN_MAX

#define SDL_ECC_RAM_WRAP_REV_REVMIN_MAX (0x0000003FU)

◆ SDL_ECC_RAM_CTRL_ECC_ENABLE_MASK

#define SDL_ECC_RAM_CTRL_ECC_ENABLE_MASK (0x00000001U)

◆ SDL_ECC_RAM_CTRL_ECC_ENABLE_SHIFT

#define SDL_ECC_RAM_CTRL_ECC_ENABLE_SHIFT (0x00000000U)

◆ SDL_ECC_RAM_CTRL_ECC_ENABLE_MAX

#define SDL_ECC_RAM_CTRL_ECC_ENABLE_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_ECC_CHECK_MASK

#define SDL_ECC_RAM_CTRL_ECC_CHECK_MASK (0x00000002U)

◆ SDL_ECC_RAM_CTRL_ECC_CHECK_SHIFT

#define SDL_ECC_RAM_CTRL_ECC_CHECK_SHIFT (0x00000001U)

◆ SDL_ECC_RAM_CTRL_ECC_CHECK_MAX

#define SDL_ECC_RAM_CTRL_ECC_CHECK_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_ENABLE_RMW_MASK

#define SDL_ECC_RAM_CTRL_ENABLE_RMW_MASK (0x00000004U)

◆ SDL_ECC_RAM_CTRL_ENABLE_RMW_SHIFT

#define SDL_ECC_RAM_CTRL_ENABLE_RMW_SHIFT (0x00000002U)

◆ SDL_ECC_RAM_CTRL_ENABLE_RMW_MAX

#define SDL_ECC_RAM_CTRL_ENABLE_RMW_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_FORCE_SEC_MASK

#define SDL_ECC_RAM_CTRL_FORCE_SEC_MASK (0x00000008U)

◆ SDL_ECC_RAM_CTRL_FORCE_SEC_SHIFT

#define SDL_ECC_RAM_CTRL_FORCE_SEC_SHIFT (0x00000003U)

◆ SDL_ECC_RAM_CTRL_FORCE_SEC_MAX

#define SDL_ECC_RAM_CTRL_FORCE_SEC_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_FORCE_DED_MASK

#define SDL_ECC_RAM_CTRL_FORCE_DED_MASK (0x00000010U)

◆ SDL_ECC_RAM_CTRL_FORCE_DED_SHIFT

#define SDL_ECC_RAM_CTRL_FORCE_DED_SHIFT (0x00000004U)

◆ SDL_ECC_RAM_CTRL_FORCE_DED_MAX

#define SDL_ECC_RAM_CTRL_FORCE_DED_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_FORCE_N_ROW_MASK

#define SDL_ECC_RAM_CTRL_FORCE_N_ROW_MASK (0x00000020U)

◆ SDL_ECC_RAM_CTRL_FORCE_N_ROW_SHIFT

#define SDL_ECC_RAM_CTRL_FORCE_N_ROW_SHIFT (0x00000005U)

◆ SDL_ECC_RAM_CTRL_FORCE_N_ROW_MAX

#define SDL_ECC_RAM_CTRL_FORCE_N_ROW_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_ERROR_ONCE_MASK

#define SDL_ECC_RAM_CTRL_ERROR_ONCE_MASK (0x00000040U)

◆ SDL_ECC_RAM_CTRL_ERROR_ONCE_SHIFT

#define SDL_ECC_RAM_CTRL_ERROR_ONCE_SHIFT (0x00000006U)

◆ SDL_ECC_RAM_CTRL_ERROR_ONCE_MAX

#define SDL_ECC_RAM_CTRL_ERROR_ONCE_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_CHECK_PARITY_MASK

#define SDL_ECC_RAM_CTRL_CHECK_PARITY_MASK (0x00000080U)

◆ SDL_ECC_RAM_CTRL_CHECK_PARITY_SHIFT

#define SDL_ECC_RAM_CTRL_CHECK_PARITY_SHIFT (0x00000007U)

◆ SDL_ECC_RAM_CTRL_CHECK_PARITY_MAX

#define SDL_ECC_RAM_CTRL_CHECK_PARITY_MAX (0x00000001U)

◆ SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MASK

#define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MASK (0x00000100U)

◆ SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_SHIFT

#define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_SHIFT (0x00000008U)

◆ SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MAX

#define SDL_ECC_RAM_CTRL_CHECK_SVBUS_TIMEOUT_MAX (0x00000001U)

◆ SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MASK

#define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MASK (0xFFFFFFFFU)

◆ SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_SHIFT

#define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_SHIFT (0x00000000U)

◆ SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MAX

#define SDL_ECC_RAM_ERR_CTRL1_ECC_ROW_MAX (0xFFFFFFFFU)

◆ SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MASK

#define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MASK (0x0000FFFFU)

◆ SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_SHIFT

#define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_SHIFT (0x00000000U)

◆ SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MAX

#define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT1_MAX (0x0000FFFFU)

◆ SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MASK

#define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MASK (0xFFFF0000U)

◆ SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_SHIFT

#define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_SHIFT (0x00000010U)

◆ SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MAX

#define SDL_ECC_RAM_ERR_CTRL2_ECC_BIT2_MAX (0x0000FFFFU)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MASK

#define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MASK (0x00000003U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_SEC_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_SHIFT (0x00000000U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MAX

#define SDL_ECC_RAM_ERR_STAT1_ECC_SEC_MAX (0x00000003U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_DED_MASK

#define SDL_ECC_RAM_ERR_STAT1_ECC_DED_MASK (0x0000000CU)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_DED_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_ECC_DED_SHIFT (0x00000002U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_DED_MAX

#define SDL_ECC_RAM_ERR_STAT1_ECC_DED_MAX (0x00000003U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MASK

#define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MASK (0x00000010U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_SHIFT (0x00000004U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MAX

#define SDL_ECC_RAM_ERR_STAT1_ECC_OTHER_MAX (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MASK

#define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MASK (0x00000060U)

◆ SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_SHIFT (0x00000005U)

◆ SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MAX

#define SDL_ECC_RAM_ERR_STAT1_PARITY_ERR_MAX (0x00000003U)

◆ SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MASK

#define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MASK (0x00000080U)

◆ SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_SHIFT (0x00000007U)

◆ SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MAX

#define SDL_ECC_RAM_ERR_STAT1_CTR_REG_ERR_MAX (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MASK

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MASK (0x00000300U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_SHIFT (0x00000008U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MAX

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_SEC_MAX (0x00000003U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MASK

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MASK (0x00000C00U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_SHIFT (0x0000000AU)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MAX

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_DED_MAX (0x00000003U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MASK

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MASK (0x00001000U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_SHIFT (0x0000000CU)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MAX

#define SDL_ECC_RAM_ERR_STAT1_CLR_ECC_OTHER_MAX (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MASK

#define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MASK (0x00006000U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_SHIFT (0x0000000DU)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MAX

#define SDL_ECC_RAM_ERR_STAT1_CLR_PARITY_ERR_MAX (0x00000003U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MASK

#define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MASK (0x00008000U)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_SHIFT (0x0000000FU)

◆ SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MAX

#define SDL_ECC_RAM_ERR_STAT1_CLR_CTRL_REG_ERR_MAX (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MASK

#define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MASK (0xFFFF0000U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_SHIFT

#define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_SHIFT (0x00000010U)

◆ SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MAX

#define SDL_ECC_RAM_ERR_STAT1_ECC_BIT1_MAX (0x0000FFFFU)

◆ SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MASK

#define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MASK (0xFFFFFFFFU)

◆ SDL_ECC_RAM_ERR_STAT2_ECC_ROW_SHIFT

#define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_SHIFT (0x00000000U)

◆ SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MAX

#define SDL_ECC_RAM_ERR_STAT2_ECC_ROW_MAX (0xFFFFFFFFU)

◆ SDL_ECC_RAM_ERR_STAT3_WB_PEND_MASK

#define SDL_ECC_RAM_ERR_STAT3_WB_PEND_MASK (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT3_WB_PEND_SHIFT

#define SDL_ECC_RAM_ERR_STAT3_WB_PEND_SHIFT (0x00000000U)

◆ SDL_ECC_RAM_ERR_STAT3_WB_PEND_MAX

#define SDL_ECC_RAM_ERR_STAT3_WB_PEND_MAX (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MASK

#define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MASK (0x00000002U)

◆ SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_SHIFT

#define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_SHIFT (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MAX

#define SDL_ECC_RAM_ERR_STAT3_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)

◆ SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MASK

#define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MASK (0x00000200U)

◆ SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_SHIFT

#define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_SHIFT (0x00000009U)

◆ SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MAX

#define SDL_ECC_RAM_ERR_STAT3_CLR_SVBUS_TIMEOUT_ERR_MAX (0x00000001U)

Data Structures

Macros