TIOVX User Guide
Data Fields
tivx_vpac_viss_params_t Struct Reference
TIOVX APIs » 1: TIOVX Public APIs » TI OpenVX Extension APIs » b: Kernels » TI VPAC VISS (Vision Imaging Sub System) Kernel APIs

The configuration data structure used by the TIVX_KERNEL_VISS kernel. More...

#include <hwa_vpac_viss1.h>

Data Fields

uint32_t sensor_dcc_id
 
uint32_t use_case
 
uint32_t fcp1_config
 
tivx_vpac_viss_fcp_params_t fcp [TIVX_VPAC_VISS_FCP_NUM_INSTANCES]
 
uint32_t output_fcp_mapping [5]
 
uint32_t bypass_cac
 
uint32_t bypass_dwb
 
uint32_t bypass_nsf4
 
uint32_t bypass_glbce
 
uint32_t h3a_in
 
uint32_t enable_ctx
 
uint32_t channel_id
 
uint32_t enable_ir_op
 
uint32_t ir_output
 
uint32_t bypass_pcid
 

Detailed Description

The configuration data structure used by the TIVX_KERNEL_VISS kernel.

Definition at line 89 of file hwa_vpac_viss1.h.

Field Documentation

◆ sensor_dcc_id

uint32_t tivx_vpac_viss_params_t::sensor_dcc_id

Identifier for DCC profile, this directly is passed to DCC parser to get the VISS configuration

Definition at line 92 of file hwa_vpac_viss1.h.

◆ use_case

uint32_t tivx_vpac_viss_params_t::use_case

Identifier corresponding to the sub-setting within the sensor configuration of the DCC file, This directly is passed to DCC parser for getting VISS configuration

Definition at line 96 of file hwa_vpac_viss1.h.

◆ fcp1_config

uint32_t tivx_vpac_viss_params_t::fcp1_config

[DONT CARE]: This is not used in TDA4VM

There are two FCP units in the VISS. FCP[0] is typically used for human vision, while FCP[1] can be used for machine vision pipeline in parallel. While the fcp[0] input is dictated by the enabling/bypassing of the upstream blocks, fcp[1] can be disabled, or configured to use an input from different tap points in the upstream processing chain. Valid values for this input are:

Enum Description
TIVX_VPAC_VISS_FCP1_DISABLED FCP1 is disabled
TIVX_VPAC_VISS_FCP1_INPUT_RFE FCP1 input is from RawFE
TIVX_VPAC_VISS_FCP1_INPUT_CAC FCP1 input is from CAC
TIVX_VPAC_VISS_FCP1_INPUT_NSF4 FCP1 input is from NSF4
TIVX_VPAC_VISS_FCP1_INPUT_GLBCE FCP1 input is from GLBCE

[DONT CARE]: This is not used in VPAC3L

Definition at line 100 of file hwa_vpac_viss1.h.

◆ fcp

tivx_vpac_viss_fcp_params_t tivx_vpac_viss_params_t::fcp

There is one FCP unit in the VPAC1 VISS. Each FCP unit has flexible multiplexing of internal taps/formats to each of their 5 output channels. This strucuture can be used to configure the signal for each of the outputs of each fcp unit, as well as other fcp specific settings.

There are two FCP units in the VISS. Each FCP unit has flexible multiplexing of internal taps/formats to each of their 5 output channels. This strucuture can be used to configure the signal for each of the outputs of each fcp unit, as well as other fcp specific settings.

There is one FCP unit in the VPAC3L VISS. Each FCP unit has flexible multiplexing of internal taps/formats to each of their 5 output channels. This strucuture can be used to configure the signal for each of the outputs of each fcp unit, as well as other fcp specific settings.

Definition at line 106 of file hwa_vpac_viss1.h.

◆ output_fcp_mapping

uint32_t tivx_vpac_viss_params_t::output_fcp_mapping

[DONT CARE]: This is not used in J721E

Mapping for FCP output to final VISS output ports.

Below table provides output format supported on different outputs for the corresponding mux value in this structure. Note that mux value is used only if the corresponding output image is set to non-null. Otherwise mux value is ignored.

val output_...[0] output_...[1] output_...[2] output_...[3] output_...[4]
0 FCP0 output0 FCP0 output1 FCP0 output0 FCP0 output1 FCP0 output4
1 FCP1 output0 FCP1 output1 FCP1 output0 FCP1 output1 FCP1 output4
2 FCP0 output2 FCP0 output3 FCP0 output2 FCP0 output3 Invalid
3 FCP1 output2 FCP1 output3 FCP1 output2 FCP1 output3 Invalid
See also
TIVX_VPAC_VISS_MAP_FCP_OUTPUT() macro to use easy to read enums instead of integer values.

Mapping for FCP output and IR output to final VISS output ports.

Other than FCP output there is one more output from PCID that is input to the final output mux. This maps the 5 outputs from FCP and 1 output from PCID to final 5 VISS outputs

Definition at line 110 of file hwa_vpac_viss1.h.

◆ bypass_cac

uint32_t tivx_vpac_viss_params_t::bypass_cac

[DONT CARE]: This is not used in J721E

Flag to enable/bypass chromatic aberation correction (CAC) processing: 1: Bypasses CAC, 0: Enables CAC

Definition at line 113 of file hwa_vpac_viss1.h.

◆ bypass_dwb

uint32_t tivx_vpac_viss_params_t::bypass_dwb

[DONT CARE]: This is not used in J721E

Flag to enable/bypass dynamic white balance (DWB) processing: 1: Bypasses DWB, 0: Enables DWB

Definition at line 116 of file hwa_vpac_viss1.h.

◆ bypass_nsf4

uint32_t tivx_vpac_viss_params_t::bypass_nsf4

Flag to enable/bypass NSF4 processing: 1: Bypasses NSF4, 0: Enables NSF4

Definition at line 120 of file hwa_vpac_viss1.h.

◆ bypass_glbce

uint32_t tivx_vpac_viss_params_t::bypass_glbce

Flag to enable/bypass GLBCE processing: 1: Bypasses GLBCE, 0: Enables GLBCE If h3a_aew_af output port of tivxVpacVissNode is not NULL, this provides input source of h3a

Valid values for this input are:

Enum Description
TIVX_VPAC_VISS_H3A_IN_RAW0 H3A Input is from RAW0
TIVX_VPAC_VISS_H3A_IN_RAW1 H3A Input is from RAW1
TIVX_VPAC_VISS_H3A_IN_RAW2 H3A Input is from RAW2
TIVX_VPAC_VISS_H3A_IN_LSC H3A Input is from LSC
Note
May change in between frames

Flag to enable/bypass GLBCE processing: 1: Bypasses GLBCE, 0: Enables GLBCE

Definition at line 124 of file hwa_vpac_viss1.h.

◆ h3a_in

uint32_t tivx_vpac_viss_params_t::h3a_in

If h3a_aew_af output port of tivxVpacVissNode is not NULL, this variable selects the h3a module to be enabled

Valid values are:

Enum Description
TIVX_VPAC_VISS_H3A_MODE_AEWB AEWB
TIVX_VPAC_VISS_H3A_MODE_AF AF

Definition at line 139 of file hwa_vpac_viss1.h.

◆ enable_ctx

uint32_t tivx_vpac_viss_params_t::enable_ctx

Enables/Disables Ctx save and restore. If enabled, the node restores the context before submitting frame to the driver and saves the context after frame completion.

Currently, Ctx save/restore is supported only for GLBCE statistics memory.

Note: It allocates additional memory for CTX and uses UDMA common channel for R5F for the memcpy.

By default, it is disabled in the init API. Application requires to enable it based on number of instances of VISS and use of GLBCE in VISS.

Definition at line 166 of file hwa_vpac_viss1.h.

◆ channel_id

uint32_t tivx_vpac_viss_params_t::channel_id

Identifier for camera channel ID. Currently not being used, potentially for future need.

Definition at line 170 of file hwa_vpac_viss1.h.

◆ enable_ir_op

uint32_t tivx_vpac_viss_params_t::enable_ir_op

There is an additional IR output from PCID block that can be passed as final output of VISS. This flag stores whether IR putput is enabled or disabled

Definition at line 121 of file hwa_vpac_viss3l.h.

◆ ir_output

uint32_t tivx_vpac_viss_params_t::ir_output

There is an additional IR output from PCID block that can be passed as final output of VISS. This stores the output format of IR output

Definition at line 125 of file hwa_vpac_viss3l.h.

◆ bypass_pcid

uint32_t tivx_vpac_viss_params_t::bypass_pcid

Flag to enable/bypass GLBCE processing: 1: Bypasses PCID, 0: Enables PCID If h3a_aew_af output port of tivxVpacVissNode is not NULL, this provides input source of h3a

Valid values for this input are:

Enum Description
TIVX_VPAC_VISS_H3A_IN_RAW0 H3A Input is from RAW0
TIVX_VPAC_VISS_H3A_IN_RAW1 H3A Input is from RAW1
TIVX_VPAC_VISS_H3A_IN_RAW2 H3A Input is from RAW2
TIVX_VPAC_VISS_H3A_IN_LSC H3A Input is from LSC
TIVX_VPAC_VISS_H3A_IN_PCID H3A Input is from PCID
Note
May change in between frames

Definition at line 155 of file hwa_vpac_viss3l.h.

The documentation for this struct was generated from the following files: