63 #ifndef TIVX_SOC_AM62A_H_    64 #define TIVX_SOC_AM62A_H_    86 #define TIVX_TARGET_MPU_0      "MPU-0"    91 #define TIVX_TARGET_MPU_1      "MPU-1"    96 #define TIVX_TARGET_MPU_2      "MPU-2"   101 #define TIVX_TARGET_MPU_3      "MPU-3"   115 #define TIVX_TARGET_DSP_C7_1    "DSP_C7-1"   122 #define TIVX_TARGET_DSP_C7_1_PRI_1    TIVX_TARGET_DSP_C7_1   128 #define TIVX_TARGET_DSP_C7_1_PRI_2    "DSP_C7-1_PRI_2"   134 #define TIVX_TARGET_DSP_C7_1_PRI_3    "DSP_C7-1_PRI_3"   140 #define TIVX_TARGET_DSP_C7_1_PRI_4    "DSP_C7-1_PRI_4"   146 #define TIVX_TARGET_DSP_C7_1_PRI_5    "DSP_C7-1_PRI_5"   152 #define TIVX_TARGET_DSP_C7_1_PRI_6    "DSP_C7-1_PRI_6"   158 #define TIVX_TARGET_DSP_C7_1_PRI_7    "DSP_C7-1_PRI_7"   164 #define TIVX_TARGET_DSP_C7_1_PRI_8    "DSP_C7-1_PRI_8"   172 #define TIVX_TARGET_DSP1        TIVX_TARGET_DSP_C7_1   180 #define TIVX_TARGET_MCU1_0      "MCU1-0"   186 #define TIVX_TARGET_DSP2        TIVX_TARGET_DSP1   194 #define TIVX_TARGET_IPU1_0      "MCU1-0"   199 #define TIVX_TARGET_CAPTURE1     "CAPTURE1"   204 #define TIVX_TARGET_CAPTURE2     "CAPTURE2"   209 #define TIVX_TARGET_CAPTURE3     "CAPTURE3"   214 #define TIVX_TARGET_CAPTURE4     "CAPTURE4"   219 #define TIVX_TARGET_VPAC_LDC1    "VPAC_LDC1"   224 #define TIVX_TARGET_VPAC_MSC1    "VPAC_MSC1"   229 #define TIVX_TARGET_VPAC_MSC2    "VPAC_MSC2"   234 #define TIVX_TARGET_VPAC_VISS1   "VPAC_VISS1"   250 typedef enum _tivx_cpu_id_e {
 
tivx_cpu_id_e
CPU ID for supported CPUs.