TIOVX User Guide
tivx_soc_am62a.h
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62 
63 #ifndef TIVX_SOC_AM62A_H_
64 #define TIVX_SOC_AM62A_H_
65 
66 #ifndef SOC_AM62A
67 #define SOC_AM62A
68 #endif
69 
70 #ifndef VPAC3L
71 #define VPAC3L
72 #endif
73 
74 #ifdef __cplusplus
75 extern "C" {
76 #endif
77 
86 #define TIVX_TARGET_MPU_0 "MPU-0"
87 
91 #define TIVX_TARGET_MPU_1 "MPU-1"
92 
96 #define TIVX_TARGET_MPU_2 "MPU-2"
97 
101 #define TIVX_TARGET_MPU_3 "MPU-3"
102 
115 #define TIVX_TARGET_DSP_C7_1 "DSP_C7-1"
116 
122 #define TIVX_TARGET_DSP_C7_1_PRI_1 TIVX_TARGET_DSP_C7_1
123 
128 #define TIVX_TARGET_DSP_C7_1_PRI_2 "DSP_C7-1_PRI_2"
129 
134 #define TIVX_TARGET_DSP_C7_1_PRI_3 "DSP_C7-1_PRI_3"
135 
140 #define TIVX_TARGET_DSP_C7_1_PRI_4 "DSP_C7-1_PRI_4"
141 
146 #define TIVX_TARGET_DSP_C7_1_PRI_5 "DSP_C7-1_PRI_5"
147 
152 #define TIVX_TARGET_DSP_C7_1_PRI_6 "DSP_C7-1_PRI_6"
153 
158 #define TIVX_TARGET_DSP_C7_1_PRI_7 "DSP_C7-1_PRI_7"
159 
164 #define TIVX_TARGET_DSP_C7_1_PRI_8 "DSP_C7-1_PRI_8"
165 
172 #define TIVX_TARGET_DSP1 TIVX_TARGET_DSP_C7_1
173 
180 #define TIVX_TARGET_MCU1_0 "MCU1-0"
181 
182 /* This is a compatibility feature used only for
183  * testing purposes and is aliased to the standalone
184  * C7 DSP
185  */
186 #define TIVX_TARGET_DSP2 TIVX_TARGET_DSP1
187 
194 #define TIVX_TARGET_IPU1_0 "MCU1-0"
195 
199 #define TIVX_TARGET_CAPTURE1 "CAPTURE1"
200 
204 #define TIVX_TARGET_CAPTURE2 "CAPTURE2"
205 
209 #define TIVX_TARGET_CAPTURE3 "CAPTURE3"
210 
214 #define TIVX_TARGET_CAPTURE4 "CAPTURE4"
215 
219 #define TIVX_TARGET_VPAC_LDC1 "VPAC_LDC1"
220 
224 #define TIVX_TARGET_VPAC_MSC1 "VPAC_MSC1"
225 
229 #define TIVX_TARGET_VPAC_MSC2 "VPAC_MSC2"
230 
234 #define TIVX_TARGET_VPAC_VISS1 "VPAC_VISS1"
235 
250 typedef enum _tivx_cpu_id_e {
251 
254 
257 
260 
263 
266 
269 
272 
273 } tivx_cpu_id_e;
274 
275 #ifdef __cplusplus
276 }
277 #endif
278 
279 #endif
Max value of CPU ID.
Invalid CPU ID.
CPU ID for DSP1.
CPU ID for C7_1.
CPU ID for MPU-0.
CPU ID for IPU1_0.
CPU ID for MCU1_0.
tivx_cpu_id_e
CPU ID for supported CPUs.