TIOVX User Guide
tivx_soc_j721e.h
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62 
63 #ifndef TIVX_SOC_J721E_H_
64 #define TIVX_SOC_J721E_H_
65 
66 #ifndef SOC_J721E
67 #define SOC_J721E
68 #endif
69 
70 #ifndef VPAC1
71 #define VPAC1
72 #endif
73 
74 #ifdef __cplusplus
75 extern "C" {
76 #endif
77 
86 #define TIVX_TARGET_MPU_0 "MPU-0"
87 
91 #define TIVX_TARGET_MPU_1 "MPU-1"
92 
96 #define TIVX_TARGET_MPU_2 "MPU-2"
97 
101 #define TIVX_TARGET_MPU_3 "MPU-3"
102 
109 #define TIVX_TARGET_DSP1 "DSP-1"
110 
117 #define TIVX_TARGET_DSP2 "DSP-2"
118 
131 #define TIVX_TARGET_DSP_C7_1 "DSP_C7-1"
132 
138 #define TIVX_TARGET_DSP_C7_1_PRI_1 TIVX_TARGET_DSP_C7_1
139 
144 #define TIVX_TARGET_DSP_C7_1_PRI_2 "DSP_C7-1_PRI_2"
145 
150 #define TIVX_TARGET_DSP_C7_1_PRI_3 "DSP_C7-1_PRI_3"
151 
156 #define TIVX_TARGET_DSP_C7_1_PRI_4 "DSP_C7-1_PRI_4"
157 
162 #define TIVX_TARGET_DSP_C7_1_PRI_5 "DSP_C7-1_PRI_5"
163 
168 #define TIVX_TARGET_DSP_C7_1_PRI_6 "DSP_C7-1_PRI_6"
169 
174 #define TIVX_TARGET_DSP_C7_1_PRI_7 "DSP_C7-1_PRI_7"
175 
180 #define TIVX_TARGET_DSP_C7_1_PRI_8 "DSP_C7-1_PRI_8"
181 
188 #define TIVX_TARGET_MCU2_0 "MCU2-0"
189 
196 #define TIVX_TARGET_IPU1_0 "MCU2-0"
197 
204 #define TIVX_TARGET_MCU2_1 "MCU2-1"
205 
212 #define TIVX_TARGET_IPU1_1 "MCU2-1"
213 
220 #define TIVX_TARGET_MCU3_0 "MCU3-0"
221 
228 #define TIVX_TARGET_MCU3_1 "MCU3-1"
229 
233 #define TIVX_TARGET_CAPTURE1 "CAPTURE1"
234 
238 #define TIVX_TARGET_CAPTURE2 "CAPTURE2"
239 
243 #define TIVX_TARGET_CAPTURE3 "CAPTURE3"
244 
248 #define TIVX_TARGET_CAPTURE4 "CAPTURE4"
249 
253 #define TIVX_TARGET_CAPTURE5 "CAPTURE5"
254 
258 #define TIVX_TARGET_CAPTURE6 "CAPTURE6"
259 
263 #define TIVX_TARGET_CAPTURE7 "CAPTURE7"
264 
268 #define TIVX_TARGET_CAPTURE8 "CAPTURE8"
269 
273 #define TIVX_TARGET_CSITX "CSITX"
274 
278 #define TIVX_TARGET_DISPLAY_M2M1 "DSS_M2M1"
279 
283 #define TIVX_TARGET_DISPLAY_M2M2 "DSS_M2M2"
284 
288 #define TIVX_TARGET_DISPLAY_M2M3 "DSS_M2M3"
289 
293 #define TIVX_TARGET_DISPLAY_M2M4 "DSS_M2M4"
294 
298 #define TIVX_TARGET_DISPLAY1 "DISPLAY1"
299 
303 #define TIVX_TARGET_DISPLAY2 "DISPLAY2"
304 
308 #define TIVX_TARGET_DMPAC_DOF "DMPAC_DOF"
309 
313 #define TIVX_TARGET_DMPAC_SDE "DMPAC_SDE"
314 
318 #define TIVX_TARGET_VPAC_LDC1 "VPAC_LDC1"
319 
323 #define TIVX_TARGET_VPAC_MSC1 "VPAC_MSC1"
324 
328 #define TIVX_TARGET_VPAC_MSC2 "VPAC_MSC2"
329 
333 #define TIVX_TARGET_VPAC_NF "VPAC_NF"
334 
338 #define TIVX_TARGET_VPAC_VISS1 "VPAC_VISS1"
339 
354 typedef enum _tivx_cpu_id_e {
355 
358 
361 
364 
367 
370 
373 
376 
379 
382 
385 
388 
391 
392 } tivx_cpu_id_e;
393 
394 
395 #ifdef __cplusplus
396 }
397 #endif
398 
399 #endif
CPU ID for MCU2_0.
Max value of CPU ID.
Invalid CPU ID.
CPU ID for DSP2.
CPU ID for MCU3_1.
CPU ID for DSP1.
CPU ID for MCU3_0.
CPU ID for C7_1.
CPU ID for IPU1_1.
CPU ID for MPU-0.
CPU ID for IPU1_0.
CPU ID for MCU2_1.
tivx_cpu_id_e
CPU ID for supported CPUs.