Introduction

API Auxilary header file for Ethernet switch module CSL.

Contains the different control command and status query functions definations

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Data Structures
struct	CSL_CPSW_VERSION
	Holds the Time sync submodule's version info. More...

struct	CSL_CPSW_CONTROL
	Holds CPSW control register contents. More...

struct	CSL_CPSW_THRURATE
	CPSW_THRU_RATE register. More...

struct	CSL_CPSW_CPPI_P0_CONTROL
	Holds CPPI P0 Control register contents. More...

struct	CSL_CPSW_CPPI_P0_RXGAP
	Holds CPPI_P0_Rx_Gap register contents. This is applicable only for 2 port switch. More...

struct	CSL_CPSW_CPPI_P0_FIFOSTATUS
	Holds CPPI_P0_FIFO_Status register contents. This is not applicable for 2 port switch. More...

struct	CSL_CPSW_CPPI_P0_HOSTBLKSPRI
	Holds CSL_CPSW_CPPI_P0_HOSTBLKSPRI register contents. This is not used for 2 port switch. More...

struct	CSL_CPSW_FLOWCNTL
	Holds flow control register contents. More...

struct	CSL_CPSW_ALE_VERSION
	Holds the ALE submodule's version info. More...

struct	CSL_CPSW_ALE_PORTCONTROL
	Holds the ALE Port control register info. More...

struct	CSL_CPSW_ALE_MCASTADDR_ENTRY
	Holds the ALE Multicast Address Table entry configuration. More...

struct	CSL_CPSW_ALE_VLANMCASTADDR_ENTRY
	Holds the ALE VLAN/Multicast Address Table entry configuration. More...

struct	CSL_CPSW_ALE_UNICASTADDR_ENTRY
	Holds the ALE Unicast Address Table entry configuration. More...

struct	CSL_CPSW_ALE_OUIADDR_ENTRY
	Holds the ALE OUI Unicast Address Table entry configuration. More...

struct	CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY
	Holds the ALE VLAN Unicast Address Table entry configuration. More...

struct	CSL_CPSW_ALE_VLAN_ENTRY
	Holds the ALE (Inner) VLAN Table entry configuration. More...

struct	CSL_CPSW_ALE_ETHERTYPE_ENTRY
	Holds the ALE Ethertype Table entry configuration. More...

struct	CSL_CPSW_ALE_IPv4_ENTRY
	Holds the ALE IPv4 Address Table entry configuration. More...

struct	CSL_CPSW_ALE_IPv6_ENTRY
	Holds the ALE IPv6 Address Table entry configuration. More...

struct	CSL_CPSW_PORTSTAT
	Holds Port Statistics Enable register contents. More...

struct	CSL_CPSW_TSCNTL
	Holds Port Time Sync Control register contents. More...

struct	CSL_CPSW_TSCONFIG
	Holds Port Time Sync Configuration contents. More...

struct	CSL_CPSW_PORT_CONTROL
	Holds CPSW Port Control contents. More...

struct	CSL_CPSW_RX_RATE_LIMIT_CONFIG
	Holds CPSW Port Rx Rate Limit Configuration for CPPI Port Ingress Rate Limitaion Operation. More...

struct	CSL_CPSW_EEE_GLOB_CONFIG
	Holds CPSW EEE (Energy Efficient Ethernet) Global Configuration. More...

struct	CSL_CPSW_EEE_PORT_CONFIG
	Holds CPSW EEE (Energy Efficient Ethernet) Per-Port Configuration. More...

struct	CSL_CPSW_EEE_PORT_STATUS
	Holds CPSW EEE (Energy Efficient Ethernet) Per-Port STATUS. More...

struct	CSL_CPSW_ALE_POLICER_GLOB_CONFIG
	Holds CPSW Policer Global Configuration. More...

struct	CSL_CPSW_ALE_CTRL2_TRUNK_CONFIG

struct	CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG

struct	CSL_CPSW_ALE_CTRL2_MALFORMEDFRAME_CONFIG

struct	CSL_CPSW_ALE_POLICER_ENTRY
	Holds the ALE Policer Table entry configuration. More...

struct	CSL_CPSW_STATS
	Holds the EMAC statistics. More...

struct	CSL_CPSW_ALE_POLICER_CONTROL

struct	CSL_CPSW_ALE_POLICER_TEST_CONTROL

struct	CSL_CPSW_ALE_POLICER_HSTAT

struct	CSL_CPSW_PTYPE
	Holds CPSW priority type register contents. More...

struct	CSL_CPSW_INTERVLANCFG
	Holds the Port intervlan configuration info. More...

struct	CSL_CPGMAC_SL_FIFOSTATUS
	Holds the Enet_Pn_FIFO_Status register contents. More...

struct	CSL_CPSW_EST_CONFIG
	Holds the Enet_Pn_EST_Control register contents. More...

Macros
#define	CSL_CPSW_ALECONTROL_RATELIMIT_EN (1 << 0u)
	ALE control register configuration definitions. More...

#define	CSL_CPSW_ALECONTROL_AUTHMODE_EN (1 << 1u)

#define	CSL_CPSW_ALECONTROL_VLANAWARE_EN (1 << 2u)

#define	CSL_CPSW_ALECONTROL_RATELIMIT_TX_EN (1 << 3u)

#define	CSL_CPSW_ALECONTROL_OUIDENY_EN (1 << 5u)

#define	CSL_CPSW_ALECONTROL_VID0MODE_EN (1 << 6u)

#define	CSL_CPSW_ALECONTROL_LEARN_NO_VID_EN (1 << 7u)

#define	CSL_CPSW_ALECONTROL_AGEOUT_NOW_EN (1 << 29u)

#define	CSL_CPSW_ALECONTROL_CLRTABLE_EN (1 << 30u)

#define	CSL_CPSW_ALECONTROL_ALE_EN (1 << 31u)

#define	CSL_CPSW_PORTMASK_PORT0_EN (1 << 0u)
	Port Mask definitions. More...

#define	CSL_CPSW_PORTMASK_PORT1_EN (1 << 1u)

#define	CSL_CPSW_PORTMASK_PORT2_EN (1 << 2u)

#define	CSL_CPSW_PORTMASK_PORT3_EN (1 << 3u)

#define	CSL_CPSW_PORTMASK_PORT4_EN (1 << 4u)

#define	CSL_CPSW_PORTMASK_PORT5_EN (1 << 5u)

#define	CSL_CPSW_PORTMASK_PORT6_EN (1 << 6u)

#define	CSL_CPSW_PORTMASK_PORT7_EN (1 << 7u)

#define	CSL_CPSW_PORTMASK_PORT8_EN (1 << 8u)

#define	CSL_ALE_ENTRYTYPE_MAC_ADDR CSL_ALE_ENTRYTYPE_ADDRESS
	ALE Table entry type: MAC ADDRESS. More...

#define	CSL_ALE_ENTRYTYPE_POLICER CSL_ALE_ENTRYTYPE_VLAN
	ALE Table entry type: POLICER ENTRY. More...

#define	CSL_CPSW_NUMALE_ENTRIES_MIN (64)

#define	CSL_CPSW_NUMSTATBLOCKS (9)

#define	CSL_ALE_TABLE_POLICER_ENUM2REG(policerType) ((policerType) << 0x1)

#define	CSL_CPSW_ALE_POLICER_PORT_VALID (1 << 0u)
	ALE Policer Entry configuration definitions. More...

#define	CSL_CPSW_ALE_POLICER_PRI_VALID (1 << 1u)

#define	CSL_CPSW_ALE_POLICER_OUI_VALID (1 << 2u)

#define	CSL_CPSW_ALE_POLICER_DST_MAC_VALID (1 << 3u)

#define	CSL_CPSW_ALE_POLICER_SRC_MAC_VALID (1 << 4u)

#define	CSL_CPSW_ALE_POLICER_OVLAN_VALID (1 << 5u)

#define	CSL_CPSW_ALE_POLICER_VLAN_VALID (1 << 6u)

#define	CSL_CPSW_ALE_POLICER_ETHERTYPE_VALID (1 << 7u)

#define	CSL_CPSW_ALE_POLICER_SRC_IP_VALID ( 1 << 8u)

#define	CSL_CPSW_ALE_POLICER_DST_IP_VALID (1 << 9u)

#define	CSL_CPSW_ALE_POLICER_THREAD_VALID ( 1 << 10u)

#define	CSL_CPSW_ALE_POLICER_PIR_VALID ( 1 << 11u)

#define	CSL_CPSW_ALE_POLICER_CIR_VALID ( 1 << 12u)

#define	CSL_CPSW_ALE_POLICER_PORT_TRUNK_VALID (1 << 13u)

#define	CSL_CPSW_ALE_POLICER_EGRESSOP_VALID (1 << 14u)

Typedefs
typedef CSL_CPSW_ALE_VLAN_ENTRY	CSL_CPSW_ALE_OUTER_VLAN_ENTRY
	Holds the ALE Outer VLAN Table entry configuration. More...

Enumerations
enum	CSL_CPSW_ALETABLE_TYPE { CSL_CPSW_ALETABLE_TYPE_4PORT, CSL_CPSW_ALETABLE_TYPE_9PORT }
	Defines ALE table types support. More...

enum	CSL_CPSW_ALE_PORTSTATE { CSL_ALE_PORTSTATE_DISABLED = 0, CSL_ALE_PORTSTATE_BLOCKED, CSL_ALE_PORTSTATE_LEARN, CSL_ALE_PORTSTATE_FORWARD }
	Defines ALE port states. More...

enum	CSL_CPSW_ALE_ENTRYTYPE { CSL_ALE_ENTRYTYPE_FREE = 0, CSL_ALE_ENTRYTYPE_ADDRESS, CSL_ALE_ENTRYTYPE_VLAN, CSL_ALE_ENTRYTYPE_VLANADDRESS }
	Defines ALE Table Entry types. More...

enum	CSL_CPSW_ALE_UCASTTYPE { CSL_ALE_UCASTTYPE_UCAST_NOAGE = 0, CSL_ALE_UCASTTYPE_UCAST_AGENOTOUCH, CSL_ALE_UCASTTYPE_UCAST_OUI, CSL_ALE_UCASTTYPE_UCAST_AGETOUCH }
	Defines ALE Unicast types. More...

enum	CSL_CPSW_ALE_ADDRTYPE { CSL_ALE_ADDRTYPE_UCAST = 0, CSL_ALE_ADDRTYPE_MCAST, CSL_ALE_ADDRTYPE_OUI }
	Defines ALE Address types. More...

enum	CSL_CPSW_ALE_POLICER_ENTRYTYPE { CSL_ALE_POLICER_ENTRYTYPE_VLAN = 0, CSL_ALE_POLICER_ENTRYTYPE_OVLAN, CSL_ALE_POLICER_ENTRYTYPE_ETHERTYPE, CSL_ALE_POLICER_ENTRYTYPE_IPV4, CSL_ALE_POLICER_ENTRYTYPE_IPV6 }
	Defines ALE Policer Entry types. More...

enum	CSL_CPSW_ALE_RAMDEPTH_E { CSL_ALE_RAMDEPTH_32 = 0, CSL_ALE_RAMDEPTH_64 = 1, CSL_ALE_RAMDEPTH_128 = 2 }
	Number of statistic blocks. More...

enum	CSL_CPSW_ALE_AGT_PRESCALE_E { CSL_ALE_AGT_PRESACLE_1M = 0, CSL_ALE_AGT_PRESACLE_1000, CSL_ALE_AGT_PRESACLE_1 }
	Defines ALE Aging Timer Prescale. More...

enum	CSL_CPSW_ALE_UPD_BW { CSL_ALE_UPD_BW_350MHZ_5M = 0, CSL_ALE_UPD_BW_359MHZ_11M, CSL_ALE_UPD_BW_367MHZ_16M, CSL_ALE_UPD_BW_375MHZ_22M, CSL_ALE_UPD_BW_384MHZ_28M, CSL_ALE_UPD_BW_392MHZ_34M, CSL_ALE_UPD_BW_400MHZ_39M, CSL_ALE_UPD_BW_409MHZ_45M }
	Defines ALE Update Bandwidth Control Value: The upd_bw_ctrl field within ALE control register specifies the rate in which adds, updates, touches, writes, and aging updates can occur. At frequencies of 350Mhz, the table update rate should be at its lowest or 5 Million updates per second. When operating the switch core at frequencies or above, the upd_bw_ctrl can be programmed more aggressive. If the upd_bw_ctrl is set but the frequency of the switch subsystem is below the associated value, ALE will drop packets due to insufficient time to complete lookup under high traffic loads. More...

enum	CSL_CPSW_ALE_POLICER_CONTROL_POLICING_MATCH_MODE { CSL_ALE_POLICER_CONTROL_POLICING_MATCH_MODE_NOMATCH_GREEN, CSL_ALE_POLICER_CONTROL_POLICING_MATCH_MODE_NOMATCH_YELLOW, CSL_ALE_POLICER_CONTROL_POLICING_MATCH_MODE_NOMATCH_RED, CSL_ALE_POLICER_CONTROL_POLICING_MATCH_MODE_NOMATCH_ENTRY0STATE }

enum	CSL_CPSW_ALE_POLICER_CONTROL_YELLOWTHRESH { CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_100, CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_50, CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_33, CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_25, CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_20, CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_17, CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_14, CSL_ALE_POLICER_CONTROL_YELLOWTHRESH_DROP_PERCENT_13 }

Functions
void	CSL_CPSW_getCpswVersionInfo (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_VERSION pVersionInfo)

Uint32	CSL_CPSW_isVlanAwareEnabled (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_enableVlanAware (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_setVlanType (CSL_Xge_cpswRegs *hCpswRegs, Uint32 vlanType)

void	CSL_CPSW_disableVlanAware (CSL_Xge_cpswRegs *hCpswRegs)

Uint32	CSL_CPSW_isPort0Enabled (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_enablePort0 (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_disablePort0 (CSL_Xge_cpswRegs *hCpswRegs)

Uint32	CSL_CPSW_isPort0PassPriTagEnabled (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_enablePort0PassPriTag (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_disablePort0PassPriTag (CSL_Xge_cpswRegs *hCpswRegs)

Uint32	CSL_CPSW_isPort1PassPriTagEnabled (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_enablePortPassPriTag (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)

void	CSL_CPSW_disablePortPassPriTag (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)

void	CSL_CPSW_getCpswControlReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CONTROL pControlRegInfo)

void	CSL_CPSW_setCpswControlReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CONTROL pControlRegInfo)

void	CSL_CPSW_getEmulationControlReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 pFree, Uint32 *pSoft)

void	CSL_CPSW_setEmulationControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 free, Uint32 soft)

void	CSL_CPSW_getPortStatsEnableReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_PORTSTAT pPortStatsCfg)

void	CSL_CPSW_setPortStatsEnableReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_PORTSTAT pPortStatsCfg)

Uint32	CSL_CPSW_isSoftIdle (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_enableSoftIdle (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_disableSoftIdle (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_getPortControlReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL pControlInfo)

void	CSL_CPSW_setPortControlReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL pControlInfo)

void	CSL_CPSW_getCppiSourceIdReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 pTxSrcId)

void	CSL_CPSW_setCppiSourceIdReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 pTxSrcId)

void	CSL_CPSW_getPort0VlanReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 pPortVID, Uint32 pPortCFI, Uint32 pPortPRI)

void	CSL_CPSW_setPort0VlanReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portVID, Uint32 portCFI, Uint32 portPRI)

void	CSL_CPSW_getPort0RxPriMapReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 pPortRxPriMap)

void	CSL_CPSW_setPort0RxPriMapReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 pPortRxPriMap)

Uint32	CSL_CPSW_getPort0FlowIdOffset (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_setPort0FlowIdOffset (CSL_Xge_cpswRegs *hCpswRegs, Uint32 flowIdOffset)

Uint32	CSL_CPSW_getPort0RxMaxLen (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_setPort0RxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 rxMaxLen)

void	CSL_CPSW_getPortBlockCountReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pRxBlkCnt_e, Uint32 pRxBlkCnt_p, Uint32 pTxBlkCnt)

Uint32	CSL_CPSW_getPortRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum)

void	CSL_CPSW_setPortRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxLen)

void	CSL_CPSW_getPortTxPriMapReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pPortTxPriMap)

void	CSL_CPSW_setPortTxPriMapReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pPortTxPriMap)

void	CSL_CPSW_getPortRxPriMapReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pPortRxPriMap)

void	CSL_CPSW_setPortRxPriMapReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pPortRxPriMap)

void	CSL_CPSW_getPortRxDscpMap (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pRxDscpPriMap)

void	CSL_CPSW_setPortRxDscpMap (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pRxDscpPriMap)

void	CSL_CPSW_getEEEGlobConfig (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG pGlobConfig)

void	CSL_CPSW_setEEEGlobConfig (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG pGlobConfig)

void	CSL_CPSW_getEEEPortConfig (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG pPortConfig)

void	CSL_CPSW_setEEEPortConfig (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG pPortConfig)

void	CSL_CPSW_EEEPortStatus (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_STATUS pPortStatus)

void	CSL_CPSW_getPortVlanReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pPortVID, Uint32 pPortCFI, Uint32 pPortPRI)

void	CSL_CPSW_setPortVlanReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 portVID, Uint32 portCFI, Uint32 portPRI)

void	CSL_CPSW_getPortMaxBlksReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pRxMaxBlks, Uint32 *pTxMaxBlks)

void	CSL_CPSW_setPortMaxBlksReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxBlks, Uint32 txMaxBlks)

void	CSL_CPSW_getPortMACAddress (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint8 pMacAddress)

void	CSL_CPSW_setPortMACAddress (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint8 pMacAddress)

void	CSL_CPSW_getPortTimeSyncCntlReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL pTimeSyncCntlCfg)

void	CSL_CPSW_setPortTimeSyncCntlReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL pTimeSyncCntlCfg)

void	CSL_CPSW_getPortTimeSyncSeqIdReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pTsLtype, Uint32 *pTsSeqIdOffset)

void	CSL_CPSW_getVlanLTypeReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 pVlanLtypeInner, Uint32 *pVlanLtypeOuter)

void	CSL_CPSW_setVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pVlanLtypeInner, Uint32 pVlanLtypeOuter)

void	CSL_CPSW_setPortTimeSyncSeqIdReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsLtype, Uint32 tsSeqIdOffset)

void	CSL_CPSW_getPortTimeSyncVlanLTypeReg (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 pTsVlanLtype1, Uint32 *pTsVlanLtype2)

void	CSL_CPSW_setPortTimeSyncVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsVlanLtype1, Uint32 tsVlanLtype2)

void	CSL_CPSW_getPortTimeSyncConfig (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG pTimeSyncConfig)

void	CSL_CPSW_setPortTimeSyncConfig (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG pTimeSyncConfig)

Uint8	CSL_CPSW_getEstTsDomain (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_setEstTsDomain (CSL_Xge_cpswRegs *hCpswRegs, Uint8 domain)

void	CSL_CPSW_getPortEstConfig (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_EST_CONFIG pEstConfig)

void	CSL_CPSW_setPortEstConfig (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_EST_CONFIG pEstConfig)

void	CSL_CPSW_writeEstFetchCmd (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 index, Uint32 fetchCount, Uint8 fetchAllow)

void	CSL_CPSW_readEstFetchCmd (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, Uint32 index, Uint32 fetchCount, Uint8 *fetchAllow)

void	CSL_CPSW_getStats (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_STATS pCpswStats)

void	CSL_CPSW_getPortStats (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_STATS pCpswStats)

void	CSL_CPSW_getRawStats (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_STATS pCpswStats)

void	CSL_CPSW_getPortRawStats (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNum, CSL_CPSW_STATS pCpswStats)

void	CSL_CPSW_getAleVersionInfo (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_VERSION pVersionInfo)

Uint32	CSL_CPSW_isAleRateLimitEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleRateLimit (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleRateLimit (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleMacAuthModeEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleMacAuthMode (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleMacAuthMode (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleVlanAwareEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleVlanAware (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleVlanAware (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleTxRateLimitEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleTxRateLimit (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleTxRateLimit (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleBypassEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleBypass (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleBypass (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleOUIDenyModeEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleOUIDenyMode (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleOUIDenyMode (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleVID0ModeEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleVID0Mode (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleVID0Mode (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleLearnNoVIDEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleLearnNoVID (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleLearnNoVID (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleUUNIToHostEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleUUNIToHost (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleUUNIToHost (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleUVLANNoLearnEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAleUVLANNoLearn (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAleUVLANNoLearn (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_getAleUpdateBW (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_setAleUpdateBW (CSL_AleRegs *hCpswAleRegs, Uint32 aleUpdBW)

void	CSL_CPSW_startAleAgeOutNow (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleAgeOutDone (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_clearAleTable (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_isAleEnabled (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_enableAle (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_disableAle (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_getAleControlReg (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_setAleControlReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleCtrlVal)

void	CSL_CPSW_getAleStatusReg (CSL_AleRegs hCpswAleRegs, Uint32 pNumPolicers, Uint32 *pNumEntries)

void	CSL_CPSW_getAleStatusNumAleEntries (CSL_AleRegs hCpswAleRegs, Uint32 pNumEntries)

CSL_CPSW_ALE_RAMDEPTH_E	CSL_CPSW_getAleStatusRamDepth (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_getAleStatusVlanMask (CSL_AleRegs hCpswAleRegs, bool vlanMsk08, bool *vlanMsk12)

Uint32	CSL_CPSW_getAlePrescaleReg (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_setAlePrescaleReg (CSL_AleRegs *hCpswAleRegs, Uint32 alePrescaleVal)

void	CSL_CPSW_getAleAgingTimerReg (CSL_AleRegs hCpswAleRegs, Uint32 pAgingPrescale, Uint32 *pAgingPeriod)

void	CSL_CPSW_setAleAgingTimerReg (CSL_AleRegs *hCpswAleRegs, Uint32 agingPrescale, Uint32 agingPeriod)

void	CSL_CPSW_getAleUnkownVlanReg (CSL_AleRegs hCpswAleRegs, Uint32 pUnVlanMemList, Uint32 pUnMcastFloodMask, Uint32 pUnRegMcastFloodMask, Uint32 *pUnForceUntagEgress)

void	CSL_CPSW_setAleUnkownVlanReg (CSL_AleRegs *hCpswAleRegs, Uint32 unVlanMemList, Uint32 unMcastFloodMask, Uint32 unRegMcastFloodMask, Uint32 unForceUntagEgress)

void	CSL_CPSW_getAleVlanMaskMuxReg (CSL_AleRegs hCpswAleRegs, Uint32 vlanMaskMux)

void	CSL_CPSW_setAleVlanMaskMuxReg (CSL_AleRegs hCpswAleRegs, Uint32 vlanMaskMux)

Int32	CSL_CPSW_getAleVlanMaskMuxEntryReg (CSL_AleRegs hCpswAleRegs, Uint32 maskMuxIndex, Uint32 vlanMaskMuxPtr)

Int32	CSL_CPSW_setAleVlanMaskMuxEntryReg (CSL_AleRegs *hCpswAleRegs, Uint32 maskMuxIndex, Uint32 vlanMaskMuxVal)

void	CSL_CPSW_getAleTableEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, Uint32 pAleInfoWd0, Uint32 pAleInfoWd1, Uint32 pAleInfoWd2)

void	CSL_CPSW_setAleTableEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, Uint32 aleInfoWd0, Uint32 aleInfoWd1, Uint32 aleInfoWd2)

CSL_CPSW_ALE_ENTRYTYPE	CSL_CPSW_getALEEntryType (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)

CSL_CPSW_ALE_ADDRTYPE	CSL_CPSW_getALEAddressType (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)

CSL_CPSW_ALE_POLICER_ENTRYTYPE	CSL_CPSW_getALEPolicerEntryType (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleMcastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleMcastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleVlanMcastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleVlanMcastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleUnicastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleUnicastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleOUIAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleOUIAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleVlanUnicastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleVlanUnicastAddrEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleVlanEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleVlanEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleOutVlanEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleOutVlanEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleEthertypeEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleEthertypeEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_getAleIPv4Entry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleIPv4Entry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType)

Uint32	CSL_CPSW_getAleIPv6HighEntryOffset (CSL_AleRegs *hCpswAleRegs)

Uint32	CSL_CPSW_getAleIPv6HighEntryIndex (CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex)

Uint32	CSL_CPSW_getAleIPv6LowEntryIndex (CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex)

void	CSL_CPSW_getAleIPv6Entry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_setAleIPv6Entry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_mapTableWord2MacAddr (uint32_t word0, uint32_t word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_mapMacAddr2TableWord (uint32_t word0, uint32_t word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType)

Uint32	CSL_CPSW_extractVid (Uint32 word1, CSL_CPSW_ALETABLE_TYPE aleType)

Uint32	CSL_CPSW_getEthertypeMax (CSL_CPSW_ALETABLE_TYPE aleType)

Uint32	CSL_CPSW_getIpv4IgnBitsMax (CSL_CPSW_ALETABLE_TYPE aleType)

Uint32	CSL_CPSW_getIpv6IgnBitsMax (CSL_CPSW_ALETABLE_TYPE aleType)

void	CSL_CPSW_clearAleEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index)

void	CSL_CPSW_getAlePortControlReg (CSL_AleRegs hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL pPortControlInfo)

void	CSL_CPSW_setAlePortControlReg (CSL_AleRegs hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL pPortControlInfo)

void	CSL_CPSW_setAlePortControlTrunk (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool trunkEnable, Uint32 trunkNum)

void	CSL_CPSW_getAlePortState (CSL_AleRegs hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE pPortState)

void	CSL_CPSW_setAlePortState (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE portState)

void	CSL_CPSW_setAlePortMirrorSouce (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool enableMirror)

void	CSL_CPSW_setMultihost (CSL_AleRegs *hCpswAleRegs, Uint32 enable)

Uint32	CSL_CPSW_getMultihost (CSL_AleRegs *hCpswAleRegs)

void	CSL_CPSW_setAleCtrl2MirrorMatchIndex (CSL_AleRegs *hCpswAleRegs, Uint32 mirrorMatchIndex)

void	CSL_CPSW_setAleCtrl2TrunkParams (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_CTRL2_TRUNK_CONFIG trunkCfg)

void	CSL_CPSW_setAleCtrl2IPPktFilterConfig (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG ipPktFltCfg)

void	CSL_CPSW_setAleCtrl2MalformedFrameConfig (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_CTRL2_MALFORMEDFRAME_CONFIG badFrmCfg)

void	CSL_CPSW_setAleIPNxtHdrWhitelist (CSL_AleRegs *hCpswAleRegs, Uint8 ipNxtHdr0, Uint8 ipNxtHdr1, Uint8 ipNxtHdr2, Uint8 ipNxtHdr3)

void	CSL_CPSW_getAlePolicerGlobConfig (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG pGlobConfig)

void	CSL_CPSW_setAlePolicerGlobConfig (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG pGlobConfig)

void	CSL_CPSW_getAlePolicerEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY pPolCfg)

void	CSL_CPSW_setAlePolicerEntry (CSL_AleRegs hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY pPolCfg)

void	CSL_CPSW_disableAlePolicerThread (CSL_AleRegs *hCpswAleRegs, Uint32 index)

void	CSL_CPSW_setAleUnknwnVlanMemberReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanMemberVal)

void	CSL_CPSW_setAleUnknwnVlanUntagReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUntagVal)

void	CSL_CPSW_setCppiP0Control (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL pCppiP0ControlCfg)

void	CSL_CPSW_setAleUnknwnVlanUnregMcastReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUnregMcastVal)

void	CSL_CPSW_setAleUnknwnVlanRegMcastReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanRegMcastVal)

void	CSL_CPSW_setAlePolicerControlReg (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL policerCntrlCfg)

void	CSL_CPSW_getAlePolicerControlReg (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL policerCntrlCfg)

void	CSL_CPSW_setAlePolicerTestControlReg (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_POLICER_TEST_CONTROL policerTestCntrlCfg)

void	CSL_CPSW_getAlePolicerHstatReg (CSL_AleRegs hCpswAleRegs, CSL_CPSW_ALE_POLICER_HSTAT policerHStatCfg)

void	CSL_CPSW_setAleOAMLpbkControl (CSL_AleRegs *hCpswAleRegs, Uint32 lpbkEnablePortMask)

void	CSL_CPSW_getAleStatusNumPolicers (CSL_AleRegs hCpswAleRegs, Uint32 pNumPolicers)

void	CSL_CPSW_setCppiPriCirEir (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 cir, Uint32 eir)

void	CSL_CPSW_getCppiPriCirEir (CSL_Xge_cpswRegs hCpswRegs, Uint32 pri, Uint32 cir, Uint32 *eir)

void	CSL_CPSW_setPriCirEir (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 cir, Uint32 eir)

void	CSL_CPSW_getPriCirEir (CSL_Xge_cpswRegs hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 cir, Uint32 *eir)

void	CSL_CPSW_setCppiRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri)

Uint8	CSL_CPSW_getCppiRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_setCppiTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getCppiTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

void	CSL_CPSW_setCppiTxDstThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getCppiDstTxThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

void	CSL_CPSW_setCppiTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getCppiTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

void	CSL_CPSW_setCppiTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getCppiTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

void	CSL_CPSW_setcppiTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri, Uint32 blks)

Uint32	CSL_CPSW_getCppiTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri)

void	CSL_CPSW_setTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri, Uint32 blks)

Uint32	CSL_CPSW_getTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)

void	CSL_CPSW_setTxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)

Uint8	CSL_CPSW_getTxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)

void	CSL_CPSW_setRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri)

Uint8	CSL_CPSW_getRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)

Uint32	CSL_CPSW_getTxHostBlksRem (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo)

void	CSL_CPSW_setTxHostBlksRem (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 txBlksRem)

void	CSL_CPSW_setTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)

void	CSL_CPSW_setTxDstThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getTxDstThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)

void	CSL_CPSW_setTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)

void	CSL_CPSW_setTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)

void	CSL_CPSW_setTxDstBasedOutFlowAddValX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 addVal)

Uint32	CSL_CPSW_getTxDstBasedOutFlowAddValX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri)

void	CSL_CPSW_setTxGlobalOutFlowThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getTxGlobalOutFlowThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

void	CSL_CPSW_setTxGlobalOutFlowThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getTxGlobalOutFlowThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

void	CSL_CPSW_setCpswTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getCpswTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

void	CSL_CPSW_setCpswTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal)

Uint32	CSL_CPSW_getCpswTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri)

Uint32	CSL_CPSW_isP0TxCastagnoliCRCEnabled (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_enableP0TxCastagnoliCRC (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_disableP0TxCastagnoliCRC (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_getPTypeReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_PTYPE pPtypeCfg)

void	CSL_CPSW_setPTypeReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_PTYPE pPtypeCfg)

void	CSL_CPSW_getThruRateReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_THRURATE pThruRateCfg)

Uint32	CSL_CPSW_getGapThreshold (CSL_Xge_cpswRegs *hCpswRegs)

void	CSL_CPSW_setGapThreshold (CSL_Xge_cpswRegs *hCpswRegs, Uint32 gapThreshold)

Uint32	CSL_CPSW_getTxStartWords (CSL_Xge_cpswRegs *hCpswRegs)

Uint32	CSL_CPSW_getTxMaxLenPerPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority)

void	CSL_CPSW_setTxMaxLenPerPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 maxLen)

void	CSL_CPSW_getCppiP0Control (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL pCppiP0ControlCfg)

void	CSL_CPSW_setCppiRxPType (CSL_Xge_cpswRegs *hCpswRegs, Uint32 p0RxPtype)

Uint32	CSL_CPSW_getCppiRxPType (CSL_Xge_cpswRegs *hCpswRegs)

Uint32	CSL_CPSW_getCppiRxPacketsPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority)

void	CSL_CPSW_setCppiRxPacketsPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 rxPackets)

void	CSL_CPSW_getCppiRxGapReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP pCppiRxGap)

void	CSL_CPSW_setCppiRxGapReg (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP pCppiRxGap)

void	CSL_CPSW_getP0FifoStatus (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CPPI_P0_FIFOSTATUS pCppiFifoStats)

void	CSL_CPSW_getP0HostBlksPri (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI pCppiHostBlksPri)

void	CSL_CPSW_setP0HostBlksPri (CSL_Xge_cpswRegs hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI pCppiHostBlksPri)

Introduction

Data Structures

Macros

Typedefs

Enumerations

Functions